Semiconductor Group

11

HYB39S16160CT-6/-7

16MBit Synchronous DRAM

± 0.3V

(Recommended Operating Conditions unless otherwise noted)

Notes:

1. The specified values are valid when addresses are changed no more than three times during trc(min.) and

when No Operation commands are registered on every rising clock edge during tRC(min).

2. The specified values are valid when data inputs (DQ’s) are stable during tRC(min.).

Parameter

Symbol

Test Condition

CAS

Latency

-6

-7

Note

max. max.

Operating Current

Icc1

Burst Length = 4

trc>=trc (min.)

tck>=tck(min.), Io = 0mA

2 bank interleave operation

150

130

mA

1, 2

Precharge

Standby Current

in Power Down

Mode

Icc2P

CKE<=VIL(max),

tck>=tck(min.)

22

mA

tCK=infinite

11

mA

Precharge

Standby Current

in Non-power

down Mode

Icc2N

CKE>=VIH(min),

tck>=tck(min.) input signals

changed once in 3 cycles

15

15

mA

CS=

High

tCK=infinite, input signals

are stable

55

mA

Active Standby

Current in Power

Down Mode

Icc3P

CKE<=VIL(max),

tck>=tck(min.)

33

mA

tCK=infinite, inpit signals

are stable

22

mA

Active Standby

Current in Non-

power Down

Mode

Icc3N

CKE>=VIH(min),

tck>=tck(min.),

changed once in 3 cycles

25

25

mA

CS=

High,

1

tCK=infinite, input signals

are stable

15

15

mA

Burst Operating

Current

Icc4

Burst Length = full page

trc = infinite

tck >= tck (min.), IO = 0 mA

2 banks activated

100

85

mA

1, 2

Auto (CBR)

Refresh Current

Icc5

trc>=trc(min)

60

50

mA

mA

1, 2

Self Refresh

Icc6

CKE=<0,2V

11

mA

1, 2