DS28E02

1-Wire FUNCTION

CONTROL

1-Wire NET

PARASITE POWER

CRC16

GENERATOR

64-BIT

ROM

64-BIT

SCRATCHPAD

512-BIT

SECURE HASH

ALGORITHM ENGINE

REGISTER

PAGE

DATA MEMORY

4 PAGES OF

256 BITS EACH

MEMORY AND

SHA-1 FUNCTION

CONTROL UNIT

Figure 1. Block Diagram

or consumable authentication and calibration, and

printer cartridge configuration and monitoring.

Overview

The block diagram in Figure 1 shows the relationships

between the major control and memory sections of the

DS28E02. The DS28E02 has six main data compo-

nents: 64-bit ROM, 64-bit scratchpad, four 256-bit

pages of EEPROM, register page, and a 512-bit SHA-1

engine. Figure 2 shows the hierarchic structure of the

1-Wire protocol. The bus master must first provide one

of the seven ROM function commands: Read ROM,

Match ROM, Search ROM, Skip ROM, Resume

Communication, Overdrive-Skip ROM, or Overdrive-

Match ROM. Upon completion of an Overdrive-Skip

ROM or Overdrive-Match ROM command executed at

standard speed, the device enters overdrive mode

where all subsequent communication occurs at a higher

speed. The protocol required for these ROM function

commands is described in Figure 10. After a ROM

function command is successfully executed, the mem-

ory and SHA-1 functions become accessible and the

master can provide any one of the 9 available function

commands. The function protocols are described in

Figure 8. All data is read and written least signifi-

cant bit first.

64-Bit ROM

Each DS28E02 contains a unique ROM registration num-

ber that is 64 bits long. The first 8 bits are a 1-Wire family

code. The next 48 bits are a unique serial number. The

last 8 bits are a cyclic redundancy check (CRC) of the

first 56 bits. See Figure 3 for details. The 1-Wire CRC is

generated using a polynomial generator consisting of a

shift register and XOR gates as shown in Figure 4. The

about the 1-Wire CRC is available in Application Note

1-Wire SHA-1 Authenticated 1Kb

EEPROM with 1.8V Operation

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ABRIDGED DATA SHEET