3.3V Spread-Spectrum EconOscillator

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11

JS2 to JS0: Jitter Percentage. These three bits select

the amount of jitter in percent. The SPRD pin must be a

logic high for the jitter to be enabled. Bit combinations

not shown are reserved.

Lo/

HiZ: Output Low or High-Z. This bit determines the

state of the output pin when the device is in power-

down mode or when the output is disabled. If Lo/

HiZ =

0, the output is

HiZ when in power-down or disabled. If

Lo/

HiZ = 1, the output is held low when in power-down

or disabled.

P3 to P0: Prescaler Divider. These bits divide the

and can be from 0 to 8. Any prescaler value entered

greater than 8 decodes as 8.

DAC (08h)

B9 to B0: DAC Setting. The DAC word sets the master

oscillator frequency to a specific value within the cur-

rent offset range. Each step of the DAC changes the

master oscillator frequency by 5kHz. The DAC word is

read and written using two-byte reads and writes

beginning at address 08h.

OFFSET (0Eh)

B4 to B0: Offset. This value selects the master oscilla-

tor frequency range that can be generated by varying

the DAC word. Valid frequency ranges are shown in

Table 2. Correct operation of the device is not guaran-

teed for values of OFFSET not shown in the table.

The default offset value (OS) is factory trimmed and

can vary from device to device. Therefore, to change

frequency range, OS must be read so the new offset

value can be calculated relative to the default. For

example, to generate a master oscillator frequency

within the largest range (61.4MHz to 66.6MHz), Table 2

indicates that the OFFSET must be programmed to OS

+ 6. This is done by reading the RANGE register and

adding 6 to the value of bits B4 to B0. The result is then

written into bits B4 to B0 of the OFFSET register.

Additional examples are provided in the

Example

Frequency Calculations section.

RANGE (37h)

B4 to B0: Range: This read-only, factory programmed

value is a copy of the factory default offset (OS). OS is

required to program new master oscillator frequencies

shown in Table 2. The read-only backup is important

because the offset register is EEPROM and is likely to

be overwritten.

ADDR (0Dh)

WC: EEPROM Write Control Bit. The WC bit

enables/disables the automatic writing of registers to

EEPROM. This prevents EEPROM wear out and elimi-

nates the EEPROM write cycle time. If WC = 0 (default),

register writes are automatically written to EEPROM. If

WC = 1, register writes are stored in SRAM and only

written into EEPROM when the user sends a WRITE EE

command. If power is cycled to the device, then the

last value stored in EEPROM is recalled. WC = 1 is

ideal for applications that frequently modify the fre-

quency/registers.

Regardless of the value of the WC bit, the value of the

ADDR register is always written immediately to EEPROM.

A2 to A0: Device Address Bits. These bits determine

the 2-wire slave address of the device. They allow up to

eight devices to be attached to the same 2-wire bus

and to be addressed individually.

WRITE EE Command (3Fh)

This command can be used when WC = 1 (see the WC

bit in ADDR register) to transfer all registers from SRAM

into EEPROM. The time required to store the values is

one EEPROM write cycle time. This command is not

needed if WC = 0.

JS2

JS1

JS0

JITTER %

000

0.5

001

1

010

2

100

4

111

8