MCM6249

6

MOTOROLA FAST SRAM

MCM6249–20

MCM6249–25

MCM6249–35

Parameter

Symbol

Min

Max

Min

Max

Min

Max

Unit

Notes

Write Cycle Time

tAVAV

20

—

25

—

35

—

ns

4

Address Setup Time

tAVEL

0

—

0

—

0

—

ns

Address Valid to End of Write

tAVEH

15

—

17

—

20

—

ns

Enable Pulse Width

tELEH,

tELWH

15

—

17

—

20

—

ns

5,6

Write Pulse Width

tWLEH

15

—

17

—

20

—

ns

Data Valid to End of Write

tDVEH

10

—

10

—

15

—

ns

Data Hold Time

tEHDX

0

—

0

—

0

—

ns

Write Recovery Time

tEHAX

0

—

0

—

0

—

ns

NOTES:

1. A write occurs during the overlap of E low and W low.

2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus con–

tention conditions during read and write cycles.

3. If G goes low coincident with or after W goes low, the output will remain in a high–impedance state.

4. All write cycle timing is referenced from the last valid address to the first transitioning address.

5. If E goes low coincident with or after W goes low, the output will remain in a high impedance condition.

6. If E goes high coincident with or before W goes high, the output will remain in a high impedance condition.

DATA VALID

HIGH–Z

tAVAV

tAVEH

tAVEL

tELWH

tEHAX

tDVEH

tEHDX

A (ADDRESS)

E (CHIP ENABLE)

W (WRITE ENABLE)

D (DATA IN)

Q (DATA OUT)

tELEH

tWLEH

ORDERING INFORMATION

(Order by Full Part Number)

Motorola Memory Prefix

Part Number

Package (WJ = 400 mil SOJ)

Full Part Numbers — MCM6249WJ20

MCM6249WJ20R2

MCM6249WJ25

MCM6249WJ25R2

MCM6249WJ35

MCM6249WJ35R2

Shipping Method (R2 = Tape and Reel, Blank = Rails)

Speed (20 = 20 ns, 25 = 25 ns, 35 = 35 ns)

MCM

6249

XX

XX

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