Semiconductor Group

10

HYB 314100BJ/BJL-50/-60/-70

3.3V 4M x 1 DRAM

Notes:

1) All voltages are referenced to

2)

3)

4) Address can be changed once or less while RAS =

a fast page mode cycle (

5) An initial pause of 200

to be a refresh cycle, before proper device operation is achieved. In case of using internal refresh counter, a

minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required.

6) AC measurements assume

7)

measured between

8) Measured with the specified current load and 100 pF at

9) Operation within the

only: If

10)Operation within the

only: If

11)Either

12)

output voltage levels.

13)

electrical characteristics only. If

open-circuit (high impedance) through the entire cycle; if

of the above sets of conditions is satisfied, the condition of the DO pin (at access time) is indeterminate.

14)These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge

in read-write cycles.