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KSZ8851-16MLLJ Datasheet(PDF) 5 Page - Micrel Semiconductor |
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KSZ8851-16MLLJ Datasheet(HTML) 5 Page - Micrel Semiconductor |
5 / 90 page Micrel, Inc. KSZ8851-16MLLJ March 2010 5 M9999-030210-1.0 LinkMD® Cable Diagnostics......................................................................................................................................... 22 Access...................................................................................................................................................................... 22 Usage ....................................................................................................................................................................... 23 Media Access Control (MAC) Operation ........................................................................................................................... 23 Inter Packet Gap (IPG) ................................................................................................................................................. 23 Back-Off Algorithm ....................................................................................................................................................... 23 Late Collision ................................................................................................................................................................ 23 Flow Control.................................................................................................................................................................. 23 Half-Duplex Backpressure............................................................................................................................................ 24 Address Filtering Function............................................................................................................................................ 24 Clock Generator ........................................................................................................................................................... 25 Bus Interface Unit (BIU)...................................................................................................................................................... 26 Supported Transfers..................................................................................................................................................... 26 Physical Data Bus Size ................................................................................................................................................ 26 Little and Big Endian Support ....................................................................................................................................... 27 Asynchronous Interface................................................................................................................................................ 27 BIU Summation ............................................................................................................................................................ 27 Queue Management Unit (QMU).................................................................................................................................. 28 Transmit Queue (TXQ) Frame Format ......................................................................................................................... 28 Frame Transmitting Path Operation in TXQ................................................................................................................. 29 Driver Routine for Transmit Packet from Host Processor to KSZ8851-16MLLJ .......................................................... 30 Receive Queue (RXQ) Frame Format.......................................................................................................................... 33 Frame Receiving Path Operation in RXQ .................................................................................................................... 33 Driver Routine for Receive Packet from KSZ8851-16MLLJ to Host Processor ........................................................... 35 In order to read received frames from RXQ without error, the software driver must use following steps:................... 36 1. When receive interrupt occurred and software driver writes “1” to clear the RX interrupt in ISR register; the KSZ8851 will update Receive Frame Counter (RXFCTR) Register for this interrupt. .................................................36 EEPROM Interface............................................................................................................................................................... 36 Loopback Support .............................................................................................................................................................. 37 Near-End (Remote) Loopback...................................................................................................................................... 37 Far-End (Local) Loopback ............................................................................................................................................ 37 CPU Interface I/O Registers ............................................................................................................................................... 38 I/O Registers................................................................................................................................................................. 38 Internal I/O Registers Space Mapping .............................................................................................................................. 39 CIDER ................................................................................................................................................................................... 43 0x8870................................................................................................................................................................................... 43 Internal I/O Registers Space Mapping (Continued) ......................................................................................................... 44 Reserved ............................................................................................................................................................................... 44 Don’t care .............................................................................................................................................................................. 44 None ...................................................................................................................................................................................... 44 Register Map: MAC, PHY and QMU................................................................................................................................... 45 Bit Type Definition ........................................................................................................................................................ 45 Chip Configuration Register (0x08 – 0x09): CCR ........................................................................................................ 45 Host MAC Address Registers: MARL, MARM and MARH ........................................................................................... 46 Host MAC Address Register Low (0x10 – 0x11): MARL.............................................................................................. 46 |
Similar Part No. - KSZ8851-16MLLJ_10 |
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Similar Description - KSZ8851-16MLLJ_10 |
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