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KSZ8895MLU Datasheet(PDF) 11 Page - Micrel Semiconductor |
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KSZ8895MLU Datasheet(HTML) 11 Page - Micrel Semiconductor |
11 / 110 page Micrel, Inc. KSZ8895MLU October 2011 11 M9999-100311-1.1 Pin Description (Continued) Pin Number Pin Name Type (1) Port Pin Function (2) 63 PMRXD2 Ipd/O 5 Reserved for MLU. Strap option: PD (default) = disable back pressure. PU = enable back pressure. 64 PMRXD1 Ipd/O 5 Reserved for MLU. Strap option: PD (default) = drop excessive collision packets. PU = does not drop excessive collision packets. 65 PMRXD0 Ipd/O 5 Reserved for MLU. Strap option: PD (default) = disable aggressive back-off algorithm in half-duplex mode. PU = enable for performance enhancement. 66 PMRXER Ipd/O 5 Reserved for MLU. Strap option: PD (default) = 1522/1518 bytes; PU = packet size up to 1536 bytes. 67 PCRS Ipd/O 5 Reserved for MLU. Strap option for port 4 only. PD (default) = force half-duplex if auto-negotiation is disabled or fails. PU = force full-duplex if auto negotiation is disabled or fails. Refer to Register 76. 68 PCOL Ipd/O 5 Reserved for MLU. Strap option for port 4 only. PD (default) = no force flow control, normal operation. PU = force flow control. Refer to Register 66. 69 SMTXEN Ipd Port 5 Switch MII transmit enable. 70 SMTXD3 Ipd Port 5 Switch MII transmit bit 3. 71 SMTXD2 Ipd Port 5 Switch MII transmit bit 2. 72 SMTXD1 Ipd Port 5 Switch MII transmit bit 1. 73 SMTXD0 Ipd Port 5 Switch MII transmit bit 0. 74 SMTXER Ipd Port 5 Switch MII transmit error. 75 SMTXC I/O Port 5 Switch MII transmit clock: Input: SW5-MII MAC mode. Output: SW5-MII PHY modes. 76 GNDD GND Digital ground. 77 VDDIO P 3.3V, 2.5V or 1.8V digital VDD for digital I/O circuitry. 78 SMRXC I/O Port 5 Switch MII receive clock: Input: SW5-MII MAC mode. Output: SW5-MII PHY mode. 79 SMRXDV Ipd/O Switch MII receive data valid. 80 SMRXD3 Ipd/O Port 5 Switch MII receive bit 3. Strap option: PD (default) = Disable Switch SW5-MII full-duplex flow control PU = Enable Switch SW5-MII full-duplex flow control. |
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