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MIC2592B Datasheet(PDF) 5 Page - Micrel Semiconductor |
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MIC2592B Datasheet(HTML) 5 Page - Micrel Semiconductor |
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5 / 31 page  March 2005 5 M9999-033105 MIC2592B Micrel Pin Description (continued) Pin Number Pin Name Pin Function 11 VSTBYA 3.3V Standby Input Voltage: Required to support PCI Express VAUX output. 26 VSTBYB Additionally, the SMBus logic and internal registers run off of VSTBY[A/B] to ensure that the chip is accessible during standby modes. A UVLO circuit prevents turn-on of this supply until VSTBY[A/B] rises above its UVLO threshold. Both pins must be externally connected together at the MIC2592B controller. 15 VAUXA 3.3VAUX[A/B] Outputs to PCI Express Card Slots: These outputs connect 22 VAUXB the 3.3AUX pin of the PCI Express connectors to VSTBY[A/B] via internal 400mΩ MOSFETs. These outputs are current limited and protected against short-circuit faults. 44 ONA Enable Inputs: Rising-edge triggered. Used to enable or disable the MAINA 43 ONB and MAINB (+3.3V and +12V) outputs. The outputs can be switched on by these controls only after the VSTBY input supply is valid and stabe (i.e., t STBY STBY POR elapses - See the Electrical Characteristics Table). Taking ON[A/B] low after a fault resets the +12V and/or +3.3V fault latches for the affected slot. Tie these pins to GND if using SMI power control. Also, see pin description for /FAULTA and /FAULTB. 45 AUXENA Enable Inputs: Rising-edge triggered. Used to enable or disable the 42 AUXENB VAUX[A/B] outputs. The outputs can be switched on by these controls only after the VSTBY input supply is valid and stabe (i.e., t STBY STBY POR elapses - See the Electrical Characteristics Table). Taking AUXEN[A/B] low after a fault resets the respective slot’s Aux Output Fault Latch. Tie these pins to GND if using SMI power control. Also, see pin description for /FAULTA and /FAULTB. 2 CFILTERA Overcurrent Timers: Capacitors connected between these 35 CFILTERB pins and GND set the duration of tFLT for each slot. The overcurrent filter delay (tFLT) is the amount of time for which a slot remains in current limit before its circuit breaker is tripped. 6 /PWRGDA /PWRGD[A/B] Outputs: Open-drain, active-low. Asserted when a slot has 31 /PWRGDB been commanded to turn on and has successfully begun delivering power to its respective +12V, +3.3V, and VAUX outputs. Each pin requires an external pull-up resistor to VSTBY. STBY STBY 1 /FAULTA /FAULT[A/B] Outputs: Open-drain, active-low. Asserted whenever the 36 /FAULTB circuit breaker trips due to a fault condition (overcurrent, input undervoltage, overtemperature). Each pin requires an external pull-up resistor to VSTBY. STBY STBY Bringing the slot’s ON[A/B] pin low resets /FAULT[A/B] if /FAULT[A/B] was asserted in response to a fault condition on one of the slot’s MAIN out- puts (+12V or +3.3V). /FAULT[A/B] is reset by bringing the slot’s AUXEN[A/B] pin low if /FAULT[A/B] was asserted in response to a fault condition on the slot’s VAUX output. If a fault condition occurred on both the MAIN and VAUX outputs of the same slot, then both ON[A/B] and AUXEN[A/B] must be brought low to deassert the /FAULT[A/B] output. 9 /FORCE_ONA Enable Inputs: Active-low, level-sensitive. Asserting a /FORCE_ON[A/B] 28 /FORCE_ONB input will turn on all three of the respective slot’s outputs (+12V, +3.3V, and VAUX), while specifically defeating all protections on those supplies. This explcitly includes all overcurrent and short circuit protections, and on-chip thermal protection for the VAUX[A/B] supplies. Additionally included are the UVLO protections for the +3.3V and +12V main supplies. The /FORCE_ON[A/B] pins do not disable UVLO protection for the VAUX[A/B] supplies. These input pins are intended for diagnostic purposes only. Asserting /FORCE_ON[A/B] will cause the respective slot’s /PWRGD[A/B] and /FAULT[A/B] pins to enter their open-drain state. Note that the SMBus register set will continue to reflect the actual state of each slot’s supplies. There is a pair of register bits, accessible via the SMBus, which can be set to disable (unconditionally deassert) either or both of the /FORCE_ON[A/B] pins -- See CNTRL[A/B] Register Bit D[2]. 4 GPI_A0 General Purpose Inputs: The states of these two inputs are available by 38 GPI_B0 reading the Common Status Register, Bits [4:5]. If not used, connect each pin to GND. Pin Number Pin Name Pin Function 26 VSTBYB Additionally, the SMBus logic and internal registers run off of VSTBY[A/B] to ensure that the chip is accessible during standby modes. A UVLO circuit prevents turn-on of this supply until VSTBY[A/B] rises above its UVLO threshold. Both pins must be externally connected together at the MIC2592B controller. 15 VAUXA 3.3VAUX[A/B] Outputs to PCI Express Card Slots: These outputs connect 22 VAUXB the 3.3AUX pin of the PCI Express connectors to VSTBY[A/B] via internal 400mΩ MOSFETs. These outputs are current limited and protected against short-circuit faults. 44 ONA Enable Inputs: Rising-edge triggered. Used to enable or disable the MAINA 43 ONB and MAINB (+3.3V and +12V) outputs. The outputs can be switched on by these controls only after the V elapses - See the Electrical Characteristics Table). Taking ON[A/B] low after a fault resets the +12V and/or +3.3V fault latches for the affected slot. Tie these pins to GND if using SMI power control. Also, see pin description for /FAULTA and /FAULTB. 45 AUXENA Enable Inputs: Rising-edge triggered. Used to enable or disable the 42 AUXENB VAUX[A/B] outputs. The outputs can be switched on by these controls only after the V Electrical Characteristics Table). Taking AUXEN[A/B] low after a fault resets the respective slot’s Aux Output Fault Latch. Tie these pins to GND if using SMI power 2 CFILTERA Overcurrent Timers: Capacitors connected between these 35 CFILTERB pins and GND set the duration of t delay (t before its circuit breaker is tripped. 31 /PWRGDB been commanded to turn on and has successfully begun delivering power to its respective +12V, +3.3V, and VAUX outputs. Each pin requires an extern pull-up resistor to V 1 /FAULTA /FAULT[A/B] Outputs: Open-drain, active-low. Asserted whenever the 36 /FAULTB circuit breaker trips due to a fault condition (overcurrent, input undervoltage, overtemperature). Each pin requires an external pull-up resistor to V Bringing the slot’s ON[A/B] pin low resets /FAULT[A/B] if /FAULT[A/B] was asserted in response to a fault condition on one of the slot’s MAIN out- puts (+12V or +3.3V). /FAULT[A/B] is reset by bringing the slot’s AUXEN[A/B] pin low if /FAULT[A/B] was asserted in response to a fault condition on the slot’s VAUX output. If a fault condition occurred on both the MAIN and VAUX outputs of the same slot, then both ON[A/B] and AUXEN[A/B] must be brought low to deassert the /FAULT[A/B] output. 9 /FORCE_ONA Enable Inputs: Active-low, level-sensitive. Asserting a /FORCE_ON[A/B] 28 /FORCE_ONB input will turn on all three of the respective slot’s outputs (+12V, +3.3V, and VAUX), while specifically defeating all protections on those supplies. This explcitly includes all overcurrent and short circuit protections, and on-chip UVLO protections for the +3.3V and +12V main supplies. The /FORCE_ON[A/B] pins do supplies. These input pins are intended for diagnostic purposes only. Asserting /FORCE_ON[A/B] will cause the respective slot’s /PWRGD[A/B] and /FAULT[A/B] pins to enter their open-drain state. Note that the SMBus register set will continue to reflect the actual state of each slot’s supplies. There is a pair of register bits, accessible via the SMBus, which can be set to disable (unconditionally deassert) either or both of the /FORCE_ON[A/B] pins -- See CNTRL[A/B] Register Bit D[2]. 4 GPI_A0 General Purpose Inputs: The states of these two inputs are available by pin to GND. Pin Number Pin Name Pin Function 11 VSTBYA 3.3V Standby Input Voltage: Required to support PCI Express VAUX output. 26 VSTBYB Additionally, the SMBus logic and internal registers run off of VSTBY[A/B] to ensure that the chip is accessible during standby modes. A UVLO circuit prevents turn-on of this supply until VSTBY[A/B] rises above its UVLO threshold. Both pins must be externally connected together at the MIC2592B controller. 15 VAUXA 3.3VAUX[A/B] Outputs to PCI Express Card Slots: These outputs connect 22 VAUXB the 3.3AUX pin of the PCI Express connectors to VSTBY[A/B] via internal 400mΩ MOSFETs. These outputs are current limited and protected against short-circuit faults. 44 ONA Enable Inputs: Rising-edge triggered. Used to enable or disable the MAINA 43 ONB and MAINB (+3.3V and +12V) outputs. The outputs can be switched on by these controls only after the V elapses - See the Electrical Characteristics Table). Taking ON[A/B] low after a fault resets the +12V and/or +3.3V fault latches for the affected slot. Tie these pins to GND if using SMI power control. Also, see pin description for /FAULTA and /FAULTB. 45 AUXENA Enable Inputs: Rising-edge triggered. Used to enable or disable the 42 AUXENB VAUX[A/B] outputs. The outputs can be switched on by these controls only after the V Electrical Characteristics Table). Taking AUXEN[A/B] low after a fault resets the respective slot’s Aux Output Fault Latch. Tie these pins to GND if using SMI power 2 CFILTERA Overcurrent Timers: Capacitors connected between these 35 CFILTERB pins and GND set the duration of t delay (t before its circuit breaker is tripped. 6 /PWRGDA /PWRGD[A/B] Outputs: Open-drain, active-low. Asserted when a slot has 31 /PWRGDB been commanded to turn on and has successfully begun delivering power to its respective +12V, +3.3V, and VAUX outputs. Each pin requires an extern pull-up resistor to V 1 /FAULTA /FAULT[A/B] Outputs: Open-drain, active-low. Asserted whenever the 36 /FAULTB circuit breaker trips due to a fault condition (overcurrent, input undervoltage, overtemperature). Each pin requires an external pull-up resistor to V Bringing the slot’s ON[A/B] pin low resets /FAULT[A/B] if /FAULT[A/B] was asserted in response to a fault condition on one of the slot’s MAIN out- puts (+12V or +3.3V). /FAULT[A/B] is reset by bringing the slot’s AUXEN[A/B] pin low if /FAULT[A/B] was asserted in response to a fault condition on the slot’s VAUX output. If a fault condition occurred on both the MAIN and VAUX outputs of the same slot, then both ON[A/B] and AUXEN[A/B] must be brought low to deassert the /FAULT[A/B] output. 9 /FORCE_ONA Enable Inputs: Active-low, level-sensitive. Asserting a /FORCE_ON[A/B] 28 /FORCE_ONB input will turn on all three of the respective slot’s outputs (+12V, +3.3V, and VAUX), while specifically defeating all protections on those supplies. This explcitly includes all overcurrent and short circuit protections, and on-chip UVLO protections for the +3.3V and +12V main supplies. The /FORCE_ON[A/B] pins do supplies. These input pins are intended for diagnostic purposes only. Asserting /FORCE_ON[A/B] will cause the respective slot’s /PWRGD[A/B] and /FAULT[A/B] pins to enter their open-drain state. Note that the SMBus register set will continue to reflect the actual state of each slot’s supplies. There is a pair of register bits, accessible via the SMBus, which can be set to disable (unconditionally deassert) either or both of the /FORCE_ON[A/B] pins -- See CNTRL[A/B] Register Bit D[2]. 4 GPI_A0 General Purpose Inputs: The states of these two inputs are available by 38 GPI_B0 reading the Common Status Register, Bits [4:5]. If not used, connect each pin to GND. Pin Number Pin Name Pin Function 11 VSTBYA 3.3V Standby Input Voltage: Required to support PCI Express VAUX output. 26 VSTBYB Additionally, the SMBus logic and internal registers run off of VSTBY[A/B] to ensure that the chip is accessible during standby modes. A UVLO circuit prevents turn-on of this supply until VSTBY[A/B] rises above its UVLO threshold. Both pins must be externally connected together at the MIC2592B controller. 15 VAUXA 3.3VAUX[A/B] Outputs to PCI Express Card Slots: These outputs connect 22 VAUXB the 3.3AUX pin of the PCI Express connectors to VSTBY[A/B] via internal 400mΩ MOSFETs. These outputs are current limited and protected against short-circuit faults. 44 ONA Enable Inputs: Rising-edge triggered. Used to enable or disable the MAINA 43 ONB and MAINB (+3.3V and +12V) outputs. The outputs can be switched on by these controls only after the V elapses - See the Electrical Characteristics Table). Taking ON[A/B] low after a fault resets the +12V and/or +3.3V fault latches for the affected slot. Tie these pins to GND if using SMI power control. Also, see pin description for /FAULTA and /FAULTB. 45 AUXENA Enable Inputs: Rising-edge triggered. Used to enable or disable the 42 AUXENB VAUX[A/B] outputs. The outputs can be switched on by these controls only after the V Electrical Characteristics Table). Taking AUXEN[A/B] low after a fault resets the respective slot’s Aux Output Fault Latch. Tie these pins to GND if using SMI power 2 CFILTERA Overcurrent Timers: Capacitors connected between these 35 CFILTERB pins and GND set the duration of t delay (t before its circuit breaker is tripped. 6 /PWRGDA /PWRGD[A/B] Outputs: Open-drain, active-low. Asserted when a slot has 31 /PWRGDB been commanded to turn on and has successfully begun delivering power to its respective +12V, +3.3V, and VAUX outputs. Each pin requires an extern pull-up resistor to V 1 /FAULTA /FAULT[A/B] Outputs: Open-drain, active-low. Asserted whenever the 36 /FAULTB circuit breaker trips due to a fault condition (overcurrent, input undervoltage, overtemperature). Each pin requires an external pull-up resistor to V Bringing the slot’s ON[A/B] pin low resets /FAULT[A/B] if /FAULT[A/B] was asserted in response to a fault condition on one of the slot’s MAIN out- puts (+12V or +3.3V). /FAULT[A/B] is reset by bringing the slot’s AUXEN[A/B] pin low if /FAULT[A/B] was asserted in response to a fault condition on the slot’s VAUX output. If a fault condition occurred on both the MAIN and VAUX outputs of the same slot, then both ON[A/B] and AUXEN[A/B] must be brought low to deassert the /FAULT[A/B] output. 9 /FORCE_ONA Enable Inputs: Active-low, level-sensitive. Asserting a /FORCE_ON[A/B] 28 /FORCE_ONB input will turn on all three of the respective slot’s outputs (+12V, +3.3V, and VAUX), while specifically defeating all protections on those supplies. This explcitly includes all overcurrent and short circuit protections, and on-chip UVLO protections for the +3.3V and +12V main supplies. The /FORCE_ON[A/B] pins do supplies. These input pins are intended for diagnostic purposes only. Asserting /FORCE_ON[A/B] will cause the respective slot’s /PWRGD[A/B] and /FAULT[A/B] pins to enter their open-drain state. Note that the SMBus register set will continue to reflect the actual state of each slot’s supplies. There is a pair of register bits, accessible via the SMBus, which can be set to disable (unconditionally deassert) either or both of the /FORCE_ON[A/B] pins -- See CNTRL[A/B] Register Bit D[2]. 4 GPI_A0 General Purpose Inputs: The states of these two inputs are available by 38 GPI_B0 reading the Common Status Register, Bits [4:5]. If not used, connect each pin to GND. |
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