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MIC5162 Datasheet(PDF) 7 Page - Micrel Semiconductor |
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MIC5162 Datasheet(HTML) 7 Page - Micrel Semiconductor |
7 / 24 page Micrel, Inc. MIC5162 March 2010 7 M9999-033110 Application Information High performance memory requires high speed signaling. This means special attention must be paid to maintain signal integrity. Bus termination provides a means to increase signaling speed while maintaining good signal integrity. An example of bus termination is the Series Stub Termination Logic or SSTL. Figure 1 is an example of an SSTL 2 single ended series parallel terminated output. SSTL 2 is a JEDEC signaling standard operating off a 2.5V supply. It consists of a series resistor (RS) and a terminating resistor (RT). Values of RS range between 10 to 30 with a typical of 22 , while RT ranges from 22 to 28 with a typical value of 25 . VREF must maintain 1/2 VDD with a ±1% tolerance, while VTT will dynamically sink and source current to maintain a termination voltage of ±40mV from the VREF line under all conditions. This method of bus termination reduces common mode noise, settling time, voltage swings, EMI/RFI and improves slew rates. The MIC5162 is a high performance linear controller, utilizing scalable N-Channel MOSFETs to provide JEDEC-compliant bus termination. Termination is achieved by dividing down the VDDQ voltage by half, providing the reference (VREF) voltage. An internal error amplifier compares the termination voltage (VTT) and VREF, controlling 2 external N-Channel MOSFETs to sink and source current to maintain a termination voltage (VTT) equal to VREF. The N-Channels receive their enhancement voltage from a separate VCC pin on the device. Although this document focuses mostly on SSTL, the MIC5162 is also capable of providing bus terminations for SCSI, GTL, HSTL, LV-TTL, Rambus, LV-PECL, DDR, DDR2, DDR3 memory termination and other systems. Figure 1. SSTL-2 Termination VDDQ The VDDQ pin on the MIC5162 provides the source current through the high-side N-Channel and the reference voltage to the device. The MIC5162 can operate at VDDQ voltages as low as 1.35V. Due to the possibility of large transient currents being sourced from this line, significant bypass capacitance will aid in performance by improving the source impedance at higher frequencies. Since the reference is simply VDDQ/2, perturbations on the VDDQ will also appear at half the amplitude on the reference. For this reason, low ESR capacitors such as ceramics or OS-CON are recommended on VDDQ. VTT VTT is the actual termination point. VTT is regulated to VREF. Due to high speed signaling, the load current seen by VTT is constantly changing. To maintain adequate large signal transient response, large OS-CON and ceramics are recommended on VTT. The proper combination and placement of the OS-CON and ceramic capacitors is important to reduce both ESR and ESL such that high-current and high-speed transients do not exceed the dynamic voltage tolerance requirement of VTT. The larger OS-CON capacitors provide bulk charge storage while the smaller ceramic capacitors provide current during the fast edges of the bus transition. Using several smaller ceramic capacitors distributed near the termination resistors is typically important to reduce the effects of PCB trace inductance. VREF Two resistors dividing down the VDDQ voltage provide VREF (Figure 3). The resistors are valued at around 17k . A minimum capacitor value of 120pF from VREF to ground is required to remove high frequency signals reflected from the source. Large capacitance values (>1500pF) should be avoided. Values greater than 1500pF slow down VREF and detract from the reference voltage’s ability to track VDDQ during high speed load transients. Figure 2. MIC5162 as a DDR Memory Termination for 3.5A Application |
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