MCM6226BB

3

MOTOROLA FAST SRAM

Characteristic

Symbol

Typ

Max

Unit

Input Capacitance

All Inputs Except Clocks and DQs

E1, E2, G, and W

Cin

Cck

4

5

6

8

pF

I/O Capacitance

DQ

CI/O

5

8

pF

AC OPERATING CONDITIONS AND CHARACTERISTICS

(VCC = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted)

Input Pulse Levels

0 to 3.0 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input Rise/Fall Time

2 ns

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input Timing Measurement Reference Level

1.5 V

. . . . . . . . . . . . . . .

Output Timing Measurement Reference Level

1.5 V

. . . . . . . . . . . . .

Output Load

See Figure 1a

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6226BB–15

6226BB–17

6226BB–20

6226BB–25

6226BB–35

Parameter

Symbol

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Unit

Notes

Read Cycle Time

tAVAV

15

—

17

—

20

—

25

—

35

—

ns

4

Address Access Time

tAVQV

—

15

—

17

—

20

—

25

—

35

ns

Enable Access Time

tELQV

—

15

—

17

—

20

—

25

—

35

ns

5

Output Enable Access Time

tGLQV

—

6

—

7

—

7

—

8

—

8

ns

Output Hold from Address

Change

tAXQX

3

—

3

—

3

—

3

—

3

—

ns

Enable Low to Output Active

tELQX

5

—

5

—

5

—

5

—

5

—

ns

6, 7, 8

Output Enable Low to Output

Active

tGLQX

0

—

0

—

0

—

0

—

0

—

ns

6, 7, 8

Enable High to Output High–Z

tEHQZ

—

6

—

7

—

7

—

8

—

8

ns

6, 7, 8

Output Enable High to Output

High–Z

tGHQZ

—

6

—

7

—

7

—

8

—

8

ns

6, 7, 8

NOTES:

1. W is high for read cycle.

2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus con-

tention conditions during read and write cycles.

3. E1 and E2 are represented by E in this data sheet. E2 is of opposite polarity to E1.

4. All timings are referenced from the last valid address to the first transitioning address.

5. Addresses valid prior to or coincident with E going low.

6. At any given voltage and temperature, tEHQZ max is less than tELQX min, and tGHQZ max is less than tGLQX min, both for a given device

and from device to device.

7. Transition is measured

± 500 mV from steady–state voltage with load of Figure 1b.

8. This parameter is sampled and not 100% tested.

9. Device is continuously selected (E

≤ VIL, G ≤ VIL).

OUTPUT

Z0 = 50 Ω

RL = 50 Ω

VL = 1.5 V

(a)

(b)

5 pF

+5 V

OUTPUT

255

Ω

480

Ω

The table of timing values shows either a

minimum or a maximum limit for each param-

eter. Input requirements are specified from

the external system point of view. Thus, ad-

dress setup time is shown as a minimum

since the system must supply at least that

much time. On the other hand, responses

from the memory are specified from the de-

vice point of view. Thus, the access time is

shown as a maximum since the device never

provides data later than that time.

TIMING LIMITS

Figure 1. AC Test Loads