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1 SY10EL35 SY100EL35 Micrel, Inc. M9999-121205 hbwhelp@micrel.com or (408) 955-1690 DESCRIPTION FEATURES JK FLIP-FLOP J K R CLK Qn+1 LL L Z Qn LH L Z L HL L Z H HH L Z Qn XX H X L NOTE: 1. Z = LOW-to-HIGH transition. SY10EL35 SY100EL35 TRUTH TABLE(1) s 525ps propagation delay s 2.2GHz toggle frequency s High bandwidth output transistions s Internal 75K Ω input pull-down resistors s Available in 8-pin SOIC package The SY10/100EL35 are high-speed JK Flip-Flops. The J/K data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave and, thus, the outputs, upon a positive transition of the clock. The reset pin is asynchronous and is activated with a logic HIGH. 1 Rev.: G Amendment: /0 Issue Date: December 2005 |
