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SY100EL15LZITR Datasheet(PDF) 1 Page - Micrel Semiconductor |
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SY100EL15LZITR Datasheet(HTML) 1 Page - Micrel Semiconductor |
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1 / 5 page  1 Precision Edge® SY100EL15L Micrel, Inc. M9999-031306 hbwhelp@micrel.com or (408) 955-1690 The SY100EL15L is a low skew 1:4 clock distribution IC designed explicitly for low skew clock distribution applications. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. If a single-ended input is to be used the VBB output should be connected to the CLK input and bypassed to ground via a 0.01 µF capacitor. The VBB output is designed to act as the switching reference for the input of the EL15 under single- ended input conditions. As a result, this pin can only source/sink up to 0.5mA of current. The EL15 features a multiplexed clock input to allow for the distribution of a lower speed scan or test clock along with the high speed system clock. When LOW (or left open and pulled LOW by the input pull-down resistor) the SEL pin will select the differential clock input. The common enable (EN) is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/ disabled as can happen with an asynchronous control. The internal flip flop is clocked on the falling edge of the input clock, therefore all associated specification limits are referenced to the negative edge of the clock input. When both differential inputs are left open, CLK input will pull down to VEE and CLK input will bias around VCC/2. Pin Function CLK Differential Clock Inputs SCLK Synchronous Clock Input EN Synchronous Enable SEL Clock Select Input VBB Reference Output Q0-3 Differential Clock Outputs TRUTH TABLE PIN NAMES FEATURES DESCRIPTION Precision Edge® SY100EL15L CLK SCLK SEL EN Q L X LLL HX L L H XL H L L XH H L H XX X H L* * On next negative transition of CLK or SCLK s 3.3V power supply s 50ps output-to-output skew s Low power s Synchronous enable/disable s Multiplexed clock input s 75K Ω internal input pull-down resistors s Available in 16-pin SOIC package 3.3V 1:4 CLOCK DISTRIBUTION 1 Rev.: D Amendment: /0 Issue Date: March 2006 Precision Edge is a registered trademark of Micrel, Inc. Precision Edge® |
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