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SY100S351

Micrel, Inc.

M9999-060910

hbwhelp@micrel.com or (408) 955-1690

BLOCK DIAGRAM

■ Max.togglefrequencyof700MHz

■ ClocktoQmax.of1200ps

■ Industrystandard100KECLlevels

■ Extendedsupplyvoltageoption:

■ Voltageandtemperaturecompensationforimproved

noiseimmunity

■ Internal75kΩinputpull-downresistors

■ 50%fasterthanFairchild300K

■ Betterthan20%lowerpowerthanFairchild

■ FunctionandpinoutcompatiblewithFairchildF100K

■ Availablein28-pinPLCCpackage

FEATURES

HEXDFLIP-FLOP

SY100S351

DESCRIPTION

The SY100S351 offers six D-type, edge-triggered, master/

slave flip-flops with differential outputs, and is designed for

use in high-performance ECL systems. The flip-flops are

controlled by the signal from the logical OR operation on a

The Master Reset (MR) input overrides all other inputs and

takes the Q outputs to a logic LOW. The inputs on this device

have 75kΩ pull-down resistors.

Rev.: I

Amendment: /0

Issue Date: June 2010

Pin

Function

Data Inputs

Common Clock Inputs

MR

Asynchronous Master Reset Input

Data Outputs

Complementary Data Outputs

PINNAMES