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SY56572XRMG Datasheet(PDF) 1 Page - Micrel Semiconductor |
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SY56572XRMG Datasheet(HTML) 1 Page - Micrel Semiconductor |
1 / 11 page SY56572XR Low Voltage 1.2V/1.8V/2.5V CML 4:1 MUX with 1:2 FANOUT 6.4Gbps with EQUALIZATION Precision Edge is a registered trademark of Micrel, Inc. Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com April 2010 M9999-041510-A hbwhelp@micrel.com or (408) 955-1690 General Description The SY56572XR is a fully differential, low voltage 1.2V/1.8V/2.5V CML 4:1 Mux, with input equalization, and integrated 1:2 Fanout Buffer. The SY56572XR can process clock signals as fast as 4.5GHz or data patterns up to 6.4Gbps. The differential input includes Micrel’s unique 3-pin input termination architecture that interfaces to DC-coupled 2.5V/3.3V LVPECL, 1.2V/1.8V/2.5V CML or LVDS differential signals. For AC-coupled input applications, an internal voltage reference is provided for input bias. Input voltages as small as 200mV (400mVpp) are applied before the 9, 18 or 27-inch FR4 transmission line. The SY56572XR operates from a 2.5V ±5% core supply and a 1.2V, 1.8V or 2.5V ±5% output supply and is guaranteed over the full industrial temperature range (–40°C to +85°C). The SY56572XR is part of Micrel’s high-speed, Precision Edge ® product line. Data sheets and support documentation can be found on Micrel’s web site at: www.micrel.com. Applications • Data Distribution • SONET clock and data distribution • Fiber Channel clock and data distribution • Gigabit Ethernet clock and data distribution Precision Edge ® Features • 1.2V/1.8V/2.5V CML 4:2 MUX with input equalization. • Guaranteed AC performance over temperature and voltage: – DC-to > 6.4Gbps throughput – <360ps propagation delay (IN-to-Q) – <15ps within-device skew • Ultra-low jitter design – <0.8psRMS random jitter – <10psPP deterministic jitter • 2.5V ±5% , 1.8/1.2V ±5% power supply operation • Industrial temperature range: –40°C to +85°C • Available in 32-pin (5mm x 5mm) QFN package Functional Block Diagram |
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