SY58039UMI datasheet(3/13 Pages) MICREL

Part #	SY58039UMI

Description	ULTRA PRECISION 8:1 MUX WITH INTERNAL TERMINATION

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Manufacturer	MICREL [Micrel Semiconductor]

Direct Link	http://www.micrel.com

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3 / 13 page

3

Precision Edge™

SY58039U

Micrel

M9999-102711

hbwhelp@micrel.com or (408) 955-1690

PACKAGE/ORDERING INFORMATION

Ordering Information(1)

Package

Operating

Package

Part Number

Type

Range

Marking

SY58039UMI

QFN-44

Industrial

SY58039U

SY58039UMITR(2)

QFN-44

Industrial

SY58039U

Notes:

1. Contact factory for die availability. Die are guaranteed at TA = 25°C,

DC electricals only.

All devices are Pb-Free.

2. Tape and Reel.

Pin Number

Pin Name

Pin Function

20, 18

IN0, /IN0,

Differential Inputs: These input pairs are the differential signal inputs to the device. Inputs

16, 14

IN1, /IN1,

accept AC- or DC-coupled signals as small as 100mV. Each pin of a pair internally terminates to

13, 11

IN2, /IN2,

a VT pin through 50ohms. Note that these inputs will default to an indeterminate state if left

9, 7

IN3, /IN3,

open. Please refer to the “Input Interface Applications” section for more details.

5, 3

IN4, /IN4,

1, 43

IN5,/IN5,

42, 40

IN6, /IN6,

38, 36

IN7, /IN7

19, 15

VT0, VT1

Input Termination Center-Tap: Each side of the differential input pair terminates to a VT pin.

12, 8

VT2, VT3,

The VT pins provide a center-tap to a termination network for maximum interface flexibility.

4, 44

VT4, VT5,

See “Input Interface Applications” section for more details. For a CML or LVDS inputs, the VT

41, 37

VT6, VT7

pin is left floating.

17

VREF-AC0,

Reference Voltage: This output biases to VCC–1.2V. It is used when AC coupling the inputs

10

VREFAC1,

(IN, /IN). For AC-coupled applications, connect VREF_AC to the VT pin and bypass with a

2

VREFAC2,

0.01μF low ESR capacitor to VCC. See “Input Interface Applications” section for more details.

39

VREF-AC3

21

SEL0,

The single-ended TTL/CMOS-compatible inputs select the inputs to the multiplexer. Note that

22

SEL1,

this input is internally connected to a 25kohms pull-up resistor and will default to a logic HIGH

35

SEL2

state if left open.

24, 27, 29, 32

VCC

Positive Power Supply. Bypass with 0.1μF

//0.01μF low ESR capacitors as close to each VCC

pin.

25, 26,

Q0,/Q0,

Differential Outputs: These 400mV LVPECL output pairs are the outputs of the device. Each

30, 31

Q1,/Q1

output is designed to drive 400mV into 50ý terminated VCC–2V (or VCC–1.2V if AC-coupled).

Unused output pairs may be left open.

23, 28, 33

GND,

Ground. GND and exposed pad must both be connected to the most negative potential of chip

Exposed Pad

ground.

PIN DESCRIPTION

1

2

3

4

5

6

7

8

33

32

31

30

29

28

27

26

12 13 14 15 16 17 18 19

44 43 42 41 40 39 38 37

IN5

VREF-AC2

/IN4

VT4

IN4

NC

/IN3

VT3

GND

VCC

/Q1

Q1

VCC

GND

VCC

/Q0

9

10

11

25

24

23

20 2122

35

IN3

VREF-AC1

/IN2

Q0

VCC

GND

36

34

44-Pin QFN (QFN-44)

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