MCM6208C

3

MOTOROLA FAST SRAM

Characteristic

Symbol

Max

Unit

Address Input Capacitance

Cin

6

pF

Control Pin Input Capacitance (E, G, W)

Cin

6

pF

I/O Capacitance

CI/O

8

pF

AC OPERATING CONDITIONS AND CHARACTERISTICS

(VCC = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted)

Input Timing Measurement Reference Level

1.5 V

. . . . . . . . . . . . . . .

Input Pulse Levels

0 to 3.0 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input Rise/Fall Time

5 ns

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output Timing Measurement Reference Level

1.5 V

. . . . . . . . . . . . .

Output Load

Figure 1A Unless Otherwise Noted

. . . . . . . . . . . . . . . .

– 12

– 15

– 20

– 25

–35

Parameter

Symbol

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Unit

Notes

Read Cycle Time

tAVAV

12

—

15

—

20

—

25

—

35

—

ns

2

Address Access Time

tAVQV

—

12

—

15

—

20

—

25

—

25

ns

Enable Access Time

tELQV

—

12

—

15

—

20

—

25

—

25

ns

3

Output Enable Access Time

tGLQV

—

6

—

8

—

10

—

12

—

—

ns

Output Hold from Address Change

tAXQX

4

—

4

—

4

—

4

—

4

—

ns

Enable Low to Output Active1

tELQX

4

—

4

—

4

—

4

—

4

—

ns

4, 5, 6

Enable High to Output High–Z

tEHQZ

0

6

0

8

0

9

0

10

0

10

ns

4, 5, 6

Output Enable Low to Output Active

tGLQX

0

—

0

—

0

—

0

—

0

—

ns

4, 5, 6

Output Enable High to Output High–Z

tGHQZ

0

6

0

7

0

8

0

10

0

—

ns

4, 5, 6

Power Up Time

tELICCH

0

—

0

—

0

—

0

—

0

—

ns

Power Down Time

tEHICCL

—

12

—

15

—

20

—

25

—

35

ns

NOTES:

1. W is high for read cycle.

2. All timings are referenced from the last valid address to the first transitioning address.

3. Addresses valid prior to or coincident with E going low.

4. At any given voltage and temperature, tEHQZ max is less than tELQX min, and tGHQZ max is less than tGLQX min, both for a given device

and from device to device.

5. Transition is measured

± 500 mV from steady–state voltage with load of Figure 1B.

6. This parameter is sampled and not 100% tested.

7. Device is continuously selected (E1

≤ VIL).

AC TEST LOADS

Figure 1A

Figure 1B

The table of timing values shows either a

minimum or a maximum limit for each param-

eter. Input requirements are specified from

the external system point of view. Thus, ad-

dress setup time is shown as a minimum

since the system must supply at least that

much time (even though most devices do not

require it). On the other hand, responses from

the memory are specified from the device

point of view. Thus, the access time is shown

as a maximum since the device never pro-

vides data later than that time.

TIMING LIMITS

OUTPUT

Z0 = 50 Ω

RL = 50 Ω

VL = 1.5 V

5 pF

+ 5 V

OUTPUT

255

Ω

480

Ω