MCM6206BB

1

MOTOROLA FAST SRAM

Product Preview

32K x 8 Bit Fast Static RAM

The MCM6206BB is a 262,144 bit static random access memory organized as

32,768 words of 8 bits. Static design eliminates the need for external clocks or

timing strobes, while CMOS circuitry reduces power consumption and provides

for greater reliability.

This device meets JEDEC standards for functionality and pinout, and is avail-

able in plastic small–outline J–leaded packages.

• Single 5 V ± 10% Power Supply

• Fully Static — No Clock or Timing Strobes Necessary

• Fast Access Times: 12/15/20/25 ns

• Equal Address and Chip Enable Access Times

• Output Enable (G) Feature for Increased System Flexibility and to

Eliminate Bus Contention Problems

• Low Power Operation: 125 – 140 mA Maximum AC

• Fully TTL Compatible — Three State Output

BLOCK DIAGRAM

AAAAAA

A

A

A

A

A

A

A

A

MEMORY MATRIX

ROW

DECODER

INPUT

DATA

CONTROL

COLUMN I/O

COLUMN DECODER

E

DQ

DQ

W

G

..

.

VCC

VSS

A

CIRCUIT

CONTROL

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.

Order this document

by MCM6206BB/D

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

PIN ASSIGNMENT

MCM6206BB

SS

A

A

A

A

A

A

A

A

A

V

V

A

A

A

CC

A

DQ

DQ

A

A

DQ

DQ

DQ

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

DQ

DQ

DQ

G

E

W

A

Address Input

. . . . . . . . . . . . . . . . . . . .

DQ

Data Input/Data Output

. . . . . . . . . .

W

Write Enable

. . . . . . . . . . . . . . . . . . . .

G

Output Enable

. . . . . . . . . . . . . . . . . . .

E

Chip Enable

. . . . . . . . . . . . . . . . . . . . . .

VCC

Power Supply (+ 5 V)

. . . . . . . . . . .

VSS

Ground

. . . . . . . . . . . . . . . . . . . . . . .

J PACKAGE

300 MIL SOJ

CASE

810B–03

PIN NAMES

6/4/97