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R5F52108ADFF Datasheet(PDF) 3 Page - Renesas Technology Corp |
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R5F52108ADFF Datasheet(HTML) 3 Page - Renesas Technology Corp |
3 / 146 page R01DS0041EJ0090 Rev.0.90 Page 3 of 144 Aug 10, 2011 RX210 Group 1. Overview Under development Preliminary document Specifications in this document are tentative and subject to change. External bus extension The external address space can be divided into four areas (CS0 to CS3), each with independent control of access settings. Capacity of each area: 16 Mbytes (CS0 to CS3) A chip-select signal (CS0# to CS3#) can be output for each area. Each area is specifiable as an 8- or 16-bit bus space The data arrangement in each area is selectable as little or big endian (only for data). Bus format: Separate bus, multiplex bus Wait control Write buffer facility DMA DMA controller (DMACA) 4 channels Three transfer modes: Normal transfer, repeat transfer, and block transfer Activation sources: Software trigger, external interrupts, and interrupt requests from peripheral functions Data transfer controller (DTC) Three transfer modes: Normal transfer, repeat transfer, and block transfer Activation sources: Interrupts Chain transfer function I/O ports Programmable I/O ports 100-pin LQFP/80-pin LQFP/64-pin LQFP I/O pin: 84/64/48 Input: 1/1/1 Pull-up resistors: 85/65/49 Open-drain outputs: 54/44/35 5-V tolerance: 4/4/2 Event link controller (ELC) Event signals of 59 types can be directly connected to the module Operations of timer modules are selectable at event input Capable of event link operation for ports B and E Multifunction pin controller (MPC) Capable of selecting input/output function from multiple pins Timers Multi-function timer pulse unit 2 (MTU2) (16 bits x 6 channels) x 1 unit Time bases for the six 16-bit timer channels can be provided via up to 16 pulse-input/output lines and three pulse-input lines Select from among eight or seven counter-input clock signals for each channel (PCLK/1, PCLK/4, PCLK/16, PCLK/64, PCLK/256, PCLK/1024, TCLKA, TCLKB, TCLKC, TCLKD) other than channel 5, for which only four signals are available. Input capture function 21 output compare/input capture registers Pulse output mode Complementary PWM output mode Reset synchronous PWM mode Phase-counting mode Generation of triggers for A/D converter conversion Port output enable2 (POE2) Controls the high-impedance state of the MTU2’s waveform output pins from multiple pins 8-bit timer (TMR) (8 bits x 2 channels) x 2 units Select from among seven internal clock signals (PCLK, PCLK/2, PCLK/8, PCLK/32, PCLK/64, PCLK/1024, PCLK/8192) and one external clock signal Capable of output of pulse trains with desired duty cycles or of PWM signals The 2 channels of each unit can be cascaded to create a 16-bit timer Capable of generating baud-rate clocks for SCI5, SCI6, and SCI12 Compare match timer (CMT) (16 bits x 2 channels) x 2 units Select from among four clock signals (PCLK/8, PCLK/32, PCLK/128, PCLK/512) Watchdog timer (WDT) 14 bits x 1 channel Select from among 6 counter-input clock signals (PCLK/4, PCLK/64, PCLK/128, PCLK/512, PCLK/2048, PCLK/8192) Independent watchdog timer (IWDT) 14 bits x 1 channel Counter-input clock: Dedicated low-speed on-chip oscillator for IWDT Frequency divided by 1, 16, 32, 64, 128, or 256 Realtime clock (RTC) Clock source: Subclock Time/calendar Interrupt sources: Alarm interrupt, periodic interrupt, and carry interrupt Time-capture facility for three values Table 1.1 Outline of Specifications (2 / 3) Classification Module/Function Description |
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