New Product

R2A20164NP/SA

Page 5 of 8

R03DS0017EJ0100 Rev.1.00

2011.09.05

AC Characteristics

Timing Chart

CLK

DI

LD

D/A

output

Do

output

(Note) Timing chart above is a schematic representation of the timing of each signal type.

CLK signal input is High or Low regardless, LD signal High input is enabled.

Symbol

MHz

10

1.0

-

Clock frequency

ns

50

-

-10

Data output delay time

4.5V,

The time until the output becomes the final

value of 1/2 LSB.

Test conditions

D/A output settling time

LD high pulse width

LD hold time

LD setup time

Data hold time

Data setup time

Clock fall time

Clock rise time

Clock high pulse width

Clock low pulse width

Item

µs

ns

ns

ns

ns

ns

ns

ns

ns

ns

Unit

Typ

Min

-

40

40

40

30

4

-

-

40

40

Limits

-

-

-

-

-

-

-

-

-

-

-

-

200

-

-

200

-

-

150

-

Max