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R2A20164SA Datasheet(PDF) 5 Page - Renesas Technology Corp |
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R2A20164SA Datasheet(HTML) 5 Page - Renesas Technology Corp |
5 / 9 page New Product R2A20164NP/SA Page 5 of 8 R03DS0017EJ0100 Rev.1.00 2011.09.05 AC Characteristics Timing Chart CLK tCR tCF tCKH tCKL tDCH tCHD tCHL tLDH tLDC tLDD DI LD D/A output tDo Do output (Note) Timing chart above is a schematic representation of the timing of each signal type. CLK signal input is High or Low regardless, LD signal High input is enabled. tLDD tDO tLDH tLDC tCHL tCHD tDCH tCF tCR tCKH tCKL fCLK Symbol MHz 10 1.0 - Clock frequency ns 50 - -10 CL< 100 pF Data output delay time Ta=25deg, CL<100pF, VAO: 0.5 4.5V, The time until the output becomes the final value of 1/2 LSB. Test conditions D/A output settling time LD high pulse width LD hold time LD setup time Data hold time Data setup time Clock fall time Clock rise time Clock high pulse width Clock low pulse width Item µs ns ns ns ns ns ns ns ns ns Unit Typ Min - 40 40 40 30 4 - - 40 40 Limits - - - - - - - - - - - - 200 - - 200 - - 150 - Max (Vcc,VrefU1,VrefU2 = +5V +/-10%, Vcc >VrefU1,VrefU2, GND=VrefL1=VrefL2= 0V, Ta= -30 to +85deg unless otherwise noted) |
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