ANALOG PRODUCTS DIVISION

561 E. Elliot Road #175 Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 632-1715

www.protekanalog.com

PA5322

100dB, 24-Bit, 192 kHz Stereo Audio CODEC

95248 Rev.0. 01/10

NOT FOR USE IN LIFE SUPPORT SYSTEMS

AUDIO DATA SAMPLING FREQUENCY AND CLOCKS

According to the input serial audio data sampling frequency, the device can work in three speed modes: single speed, double speed

or quad speed modes. The ranges of the sampling frequency in these three modes are listed in Table1.

ADCSampleRate bits in ADC Control 2 register (RAM address 0x02) or DACSampleRate bits in DAC Control 2 register (RAM

address 0x07) set the speed mode.

By default, the device can detect the speed mode automatically when sampling rate falls within the Fs Auto Detection Ranges listed in

Table1.

In this auto detection mode, sampling frequency outside the specified ranges is not supported. ADC and DAC have separate auto

detection so ADC and DAC sampling frequencies can be completely independent.

Table 1. Sampling Frequency and CLK/LRCK Ration

Speed Mode

Sampling Frequency

Fs Auto Detection Range

MCLK/LRCK Ratio

Single Speed

8kHz – 50kHz

8kHz – 50kHz

256, 384, 512, 768, 1024

Double Speed

50kHz – 100kHz

84kHz – 100kHz

128, 192, 256, 384, 512

Quad Speed

100kHz – 200kHz

167kHz – 200kHz

128, 192, 256

The device uses separate master clocks, LRCK clocks and SCLK clocks for the ADC and DAC. The allowed MCLK/LRCK ratios in

each speed mode are also listed in Table1. The device always detects MCLK/LRCK ratio automatically.

HARDWARE MODE

The device can operate in the hardware mode or the software mode. The default is the hardware mode. To change the hardware

mode to the software mode, set SCPEn bit of Chip Control register (RAM address 0x00) to 1.

In the hardware mode, pin M3 sets I

and pins M1 and pin M0 select one of the four ADC analog inputs.

Please refer to PIN DESCRIPTIONS section for detail settings.

POWER UP AND DOWN

The chip internal power on reset will reset the device when VDDD ramps from ground to supply voltage level. When VDDD and VDDA

are present to the device, applying ADCMCLK and ADCLRCK will startup the ADC and applying DACMCLK and DACLRCK will start

up the DAC.

During the DAC startup, DAC analog outputs ramp gradually from ground to mid level to minimize audible pop noise. This gradual

ramp feature can be turned off by setting ClickFree bit of DAC Control 1 register (RAM address 0x06) to 0.

ADC and DAC can power up or down independently. In the software mode, ADC or DAC can power down through ADCPDN bit or

DACPDN bit of Chip Control register (RAM address 0x00). In the hardware mode, ADC can power down by stopping ADCMCLK or

ADCLRCK, and DAC can power down by stopping DACMCLK or DACLRCK.

MICRO-CONTROLLER CONFIGURATION INTERFACE

The device supports standard SPI and 2-wire micro-controller configuration interface. External micro-controller can completely

configure the device through writing to internal configuration registers.

The identical device pins are used to configure either SPI or 2-wire interface. In SPI mode, pin CE, CCLK and CDATA function as

SPI_CSn, SPI_CLK and SPI_DIN. In 2-wire mode, pin CE, CCLK and CDATA function as AD0, SCL and SDA.

To select SPI mode, apply high to low transition signal to CE pin. Otherwise the device will operate in 2-wire interface mode.

SPI

PA5322 has a SPI (Serial Peripheral Interface) compliant synchronous serial slave controller inside the chip. It provides the ability to

allow the external master SPI controller to access the internal registers, and thus control the operations of chip.

All lines on the SPI bus are unidirectional: The SPI_CLK is generated by the master controller and is primarily used to synchronize

data transfer, the SPI_DIN line carries data from the master to the slave; SPI_CSn is generated by the master to select PA5322.

The timing diagram of this interface is given in Figure 1. The high to low transition at SPI_CSn pin indicates the SPI interface

selected. Each write procedure contains 3 words, i.e. Chip Address plus R/W bit, internal register address and internal register data.

Every word length is fixed at 8 bits. The input SPI_DIN data are sampled at the rising edge of SPI_CLK clock. The MSB bit in each

word is transferred firstly. The transfer rate can be up to 10M bps.