Atmel AT88SA10HS [DATASHEET]

11

8595G

−CRYPTO−9/11

5.4.2

Synchronization Procedures

When the system and the AT88SA10HS fall out of synchronization, the system will ultimately end up sending a Transmit flag

which will not generate a response from the AT88SA10HS. The system should implement its own timeout which waits for

It may be possible that the system does not get the 0x11 code from the AT88SA10HS for one of the following reasons:

1.

and re-issue the Wake token.

2.

The AT88SA10HS went into the sleep mode for some reason while the system was transmitting data. In this case, the

AT88SA10HS will interpret the next data bit as a Wake token, but ignore some of the subsequently transmitted bits

during its wake-up delay. If any bytes are transmitted after the wake-up delay, they may be interpreted as a legal flag,

though the following bytes would not be interpreted as a legal command due to an incorrect count or the lack of a

3.

interval, see below. There is no way to externally reset the AT88SA10HS – the system should leave the IO pin idle for

this interval and issue the Wake token.

5.5

Watchdog Failsafe

the chip will enter sleep mode, regardless of whether it is in the middle of execution of a command and/or whether some IO

transmission is in progress. There is no way to reset the counter other than to put the chip to sleep and wake it up again.

This is implemented as a fail-safe so that no matter what happens on either the system side or inside the various state

machines of the AT88SA10HS including any IO synchronization issue, power consumption will fall to the low sleep level

automatically.

5.6

Byte and Bit Ordering

The AT88SA10HS is a little-endian chip:

received