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AD7606 Datasheet(PDF) 8 Page - Analog Devices |
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AD7606 Datasheet(HTML) 8 Page - Analog Devices |
8 / 32 page AD7608 Data Sheet Rev. A | Page 8 of 32 Limit at TMIN, TMAX Parameter Min Typ Max Unit Description t27 Delay from AA RDEE AA falling edge to FRSTDATA low 19 ns VDRIVE = 3.3 V to 5.25 V 24 ns VDRIVE = 2.3 V to 2.7 V t28 Delay from 16th SCLK falling edge to FRSTDATA low 17 ns VDRIVE = 3.3 V to 5.25 V 22 ns VDRIVE = 2.3 V to 2.7 V t29 24 ns Delay from AA CSEE AA rising edge until FRSTDATA three-state enabled 1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. 2 The delay between the CONVST x signals was measured as the maximum time allowed while ensuring a <40 LSB performance matching between channel sets. 3 A buffer is used on the data output pins for these measurements, which is equivalent to a load of 20 pF on the output pins. Timing Diagrams tCYCLE t3 t5 t2 t4 t1 t7 tRESET tCONV CONVST A/ CONVST B CONVST A/ CONVST B BUSY CS RESET Figure 2.CONVST x Timing—Reading After a Conversion tCYCLE t3 t5 t6 t2 t1 tCONV CONVST A/ CONVST B CONVST A/ CONVST B BUSY CS t7 tRESET RESET Figure 3. CONVST x Timing—Reading During a Conversion DATA: DB[15:0] FRSTDATA CS RD INVALID V1 [17:2] V1 [1:0] V2 [17:2] V8 [17:2] V8 [1:0] V2 [1:0] t10 t8 t13 t24 t26 t27 t14 t11 t9 t16 t17 t29 t15 Figure 4. Parallel Mode Separate AA CSEE AA and AA RDEE AA Pulses |
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