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C165 Semiconductor Group 42 Figure 13-3 External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Normal ALE Data Out Data In t 38 Address ALE CSx A23-A16 A15-A0 BHE Read Cycle RD RdCSx Write Cycle WrCSx t 5 t 16 t 17 t 6 t 39 t 41 t 26 t 28 t 18 t 21 t 15 t 47 t 13 t 49 t 22 t 24 t 13 t 49 t 9 t 43 t 43 t 9 t 50 t 51 t 55 t 68 t 57 BUS (D15-D8) D7-D0 BUS (D15-D8) D7-D0 WR, WRL, WRH |
