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74LVC1G74GM Datasheet(PDF) 5 Page - NXP Semiconductors |
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74LVC1G74GM Datasheet(HTML) 5 Page - NXP Semiconductors |
5 / 25 page 74LVC1G74 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 10 — 2 December 2011 5 of 25 NXP Semiconductors 74LVC1G74 Single D-type flip-flop with set and reset; positive edge trigger 6.2 Pin description 7. Functional description [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care. [1] H = HIGH voltage level; L = LOW voltage level; = LOW-to-HIGH CP transition; Qn+1 = state after the next LOW-to-HIGH CP transition. Table 3. Pin description Symbol Pin Description SOT505-2, SOT765-1, SOT833-1, SOT1089, SOT996-2, SOT1116 and SOT1203 SOT902-1 CP 1 7 clock input (LOW-to-HIGH, edge-triggered) D 2 6 data input Q 3 5 complement output GND 4 4 ground (0 V) Q 5 3 true output RD 6 2 asynchronous reset-direct input (active LOW) SD 7 1 asynchronous set-direct input (active LOW) VCC 8 8 supply voltage Table 4. Function table for asynchronous operation[1] Input Output SD RD CP D Q Q L H XXH L H L XXL H L L XXH H Table 5. Function table for synchronous operation[1] Input Output SD RD CP D Qn+1 Qn+1 HH LLH HH HHL |
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