AD9628-125EBZ datasheet(9/44 Pages) AD

Part #	AD9628-125EBZ

Description	12-Bit, 125/105 MSPS, 1.8 V Dual Analog-to-Digital Converter

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Manufacturer	AD [Analog Devices]

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AD9628

Rev. 0 | Page 9 of 44

TIMING SPECIFICATIONS

Table 5.

Parameter

Description

Limit

Unit

SYNC TIMING

REQUIREMENTS

t

SSYNC

SYNC to rising edge of CLK+ setup time

0.24

ns typ

t

HSYNC

SYNC to rising edge of CLK+ hold time

0.40

ns typ

SPI TIMING

REQUIREMENTS

t

DS

Setup time between the data and the rising edge of SCLK

2

ns min

t

DH

Hold time between the data and the rising edge of SCLK

2

ns min

t

CLK

Period of the SCLK

40

ns min

t

S

Setup time between CSB and SCLK

2

ns min

t

H

Hold time between CSB and SCLK

2

ns min

t

HIGH

SCLK pulse width high

10

ns min

t

LOW

SCLK pulse width low

10

ns min

t

EN_SDIO

Time required for the SDIO pin to switch from an input to an output relative

to the SCLK falling edge

10

ns min

t

DIS_SDIO

Time required for the SDIO pin to switch from an output to an input relative

to the SCLK rising edge

10

ns min

Timing Diagrams

tPD

tSKEW

tCH

tDCO

tCLK

N – 16

N – 17

N – 1

N + 1

N + 2

N + 3

N + 5

N + 4

N

N – 15

N – 14

N – 13

N – 12

VIN

CLK+

CLK–

CH A/CH B DATA

DCOA/DCOB

tA

Figure 2. CMOS Default Output Mode Data Output Timing

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AD9628-125EBZ Datasheet(PDF) 9 Page - Analog Devices

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