Wide Input Voltage Range, High Efficiency

Fault Tolerant LED Driver

A8513

3

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

LP Package

LY Package

Pin-out Diagram

Terminal List Table

Name

Number

Function

LP

LY

COMP

15

10

Output of the error amplifier and compensation node. Connect compensation network from

this pin to GND for control loop compensation.

¯F¯¯A¯¯¯U¯¯L¯¯T¯

64

This pin is used to indicate fault conditions. Logic low indicates that the A8513 has

a fault present.

GND

13,14

9

Ground.

ISET

12

8

LED

10

6

Connect the cathode of the LED string to this pin.

NC

1,2,8,9,16

–

No connection.

OVP

4

2

This pin is used to sense an overvoltage condition. Connect a resistive divider from the

VOUT node to this pin to adjust the Overvoltage Protection (OVP).

PAD

–

–

Exposed pad of the package providing enhanced thermal dissipation. This pad must be

connected to the ground plane(s) of the PCB with at least 8 thermal vias, directly in the pad.

EN/PWM

11

7

PWM dimming pin. Used to control LED intensity by using pulse width modulation.

SW

3

1

The drain of the internal NMOS switch of the boost converter.

VDD

7

5

Output of internal LDO. Connect a 0.1 μF decoupling capacitor between this pin and GND.

VIN

5

3

Input power to the A8513.

SW

OVP

VIN

FAULT

VDD

COMP

GND

ISET

EN/PWM

LED

1

2

3

4

5

10

9

8

7

6

PAD

NC

NC

SW

OVP

VIN

FAULT

VDD

NC

NC

COMP

GND

GND

ISET

EN/PWM

LED

NC

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

PAD

Characteristic

Symbol

Test Conditions*

Value

Unit

Package Thermal Resistance

(Junction to Ambient)

LP package

On 4-layer PCB based on JEDEC standard

34

ºC/W

43

ºC/W

LY package

On 4-layer PCB based on JEDEC standard

48

ºC/W

48

ºC/W

Package Thermal Resistance

(Junction to Pad)

2

ºC/W