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A1150 Datasheet(PDF) 9 Page - Allegro MicroSystems

Part # A1150
Description  Chopper-Stabilized, Two Wire Hall-Effect Switches
Download  12 Pages
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Manufacturer  ALLEGRO [Allegro MicroSystems]
Direct Link  http://www.allegromicro.com
Logo ALLEGRO - Allegro MicroSystems

A1150 Datasheet(HTML) 9 Page - Allegro MicroSystems

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Chopper-Stabilized, Two Wire
Hall-Effect Switches
A1150, A1152, A1153, A1155,
A1156, A1157, and A1158
9
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
The device must be operated below the maximum junction tem-
perature of the device, TJ(max). Under certain combinations of
peak conditions, reliable operation may require derating supplied
power or improving the heat dissipation properties of the appli-
cation. This section presents a procedure for correlating factors
affecting operating TJ. (Thermal data is also available on the
Allegro MicroSystems Web site.)
The Package Thermal Resistance, RJA, is a figure of merit sum-
marizing the ability of the application and the device to dissipate
heat from the junction (die), through all paths to the ambient air.
Its primary component is the Effective Thermal Conductivity, K,
of the printed circuit board, including adjacent devices and traces.
Radiation from the die through the device case, RJC, is relatively
small component of RJA. Ambient air temperature, TA, and air
motion are significant external factors, damped by overmolding.
The effect of varying power levels (Power Dissipation, PD), can
be estimated. The following formulas represent the fundamental
relationships used to estimate TJ, at PD.
PD = VIN
× IIN
(1)
T = PD
× RJA
(2)
TJ = TA + ΔT
(3)
For example, given common conditions such as: TA= 25°C,
VCC = 12 V, ICC = 4 mA, and RJA = 140 °C/W, then:
PD = VCC
× ICC = 12 V × 4 mA = 48 mW
T = PD
× RJA = 48 mW × 140 °C/W = 7°C
TJ = TA + T = 25°C + 7°C = 32°C
A worst-case estimate, PD(max), represents the maximum allow-
able power level (VCC(max), ICC(max)), without exceeding
TJ(max), at a selected RJA and TA.
Example: Reliability for VCC at TA=150°C, package UA, using a
low-K PCB.
Observe the worst-case ratings for the device, specifically:
RJA=165 °C/W, TJ(max) =165°C, VCC(max)= 24 V, and
ICC(max) = 17 mA.
Calculate the maximum allowable power level, PD(max). First,
invert equation 3:
Tmax = TJ(max) – TA = 165°C–150°C = 15°C
This provides the allowable increase to TJ resulting from internal
power dissipation. Then, invert equation 2:
PD(max) = Tmax÷RJA =15°C÷165 °C/W=91mW
Finally, invert equation 1 with respect to voltage:
VCC(est) = PD(max) ÷ ICC(max)= 91mW÷17 mA=5 V
The result indicates that, at TA, the application and device can
dissipate adequate amounts of heat at voltages ≤VCC(est).
Compare VCC(est) to VCC(max). If VCC(est) ≤ VCC(max), then reli-
able operation between VCC(est) and VCC(max) requires enhanced
RJA. If VCC(est) ≥ VCC(max), then operation between VCC(est)
and VCC(max) is reliable under these conditions.
Power Derating


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