19-Output Differential Zbuffer for PCIe Gen2/3 and QPI

1586J - 12/08/11

9ZX21901B

19-Output Differential Zbuffer for PCIe Gen2/3 and QPI

7

Electrical Characteristics - Current Consumption

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

NOTES

Operating Supply Current

407

500

mA

1

Powerdown Current

All differential pairs tri-stated

12

36

mA

1

Electrical Characteristics - Skew and Differential Jitter Parameters

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

NOTES

CLK_IN, DIF[x:0]

Input-to-Output Skew in PLL mode

nominal value @ 25°C, 3.3V

-300

-200

-100

ps

1,2,4,5,8

CLK_IN, DIF[x:0]

Input-to-Output Skew in Bypass mode

nominal value @ 25°C, 3.3V

2.5

3.5

4.5

ns

1,2,3,5,8

CLK_IN, DIF[x:0]

Input-to-Output Skew Varation in PLL mode

across voltage and temperature

-50

0

50

ps

1,2,3,5,8

CLK_IN, DIF[x:0]

Input-to-Output Skew Varation in Bypass mode

across voltage and temperature

-250

250

ps

1,2,3,5,8

CLK_IN, DIF[x:0]

Random Differential Tracking error beween two

9ZX devices in Hi BW Mode

35

ps

(rms)

1,2,3,5,8

CLK_IN, DIF[x:0]

Random Differential Spread Spectrum Tracking

error beween two 9ZX devices in Hi BW Mode

15

75

ps

1,2,3,5,8

DIF{x:0]

Output-to-Output Skew across all outputs

(Common to Bypass and PLL mode)

45

65

ps

1,2,3,8

PLL Jitter Peaking

LOBW#_BYPASS_HIBW = 1

0

1

2.5

dB

7,8

PLL Jitter Peaking

LOBW#_BYPASS_HIBW = 0

0

1

2

dB

7,8

PLL Bandwidth

LOBW#_BYPASS_HIBW = 1

2

3

4

MHz

8,9

PLL Bandwidth

LOBW#_BYPASS_HIBW = 0

0.7

1

1.4

MHz

8,9

Duty Cycle

Measured differentially, PLL Mode

45

50

55

%

1

Duty Cycle Distortion

Measured differentially, Bypass Mode

@100MHz

-2

0

2

%

1,10

PLL mode

24

50

ps

1,11

Additive Jitter in Bypass Mode

20

50

ps

1,11

Notes for preceding table:

path is 695 mils long.

Jitter, Cycle to cycle