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9LPRS502YGLFT Datasheet(PDF) 10 Page - Integrated Device Technology |
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9LPRS502YGLFT Datasheet(HTML) 10 Page - Integrated Device Technology |
10 / 29 page IDTTM/ICSTM 56-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor 1125E—02/26/09 Advance Information ICS9LPRS502 56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR 10 MLF Pin Description (Continued) PIN # PIN NAME TYPE DESCRIPTION 43 VDDSRC_IO PWR Power supply for SRC outputs. 1.05 to 3.3V +/-5%. 44 CPUC2_ITP/SRCC8 OUT Complement clock of low power differential CPU2/Complement clock of differential SRC pair. The function of this pin is determined by the latched input value on pin 7, PCIF5/ITP_EN on powerup. The function is as follows: Pin 7 latched input Value 0 = SRC8# 1 = ITP# 45 CPUT2_ITP/SRCT8 OUT True clock of low power differential CPU2/True clock of differential SRC pair. The function of this pin is determined by the latched input value on pin 7, PCIF5/ITP_EN on powerup. The function is as follows: Pin 7 latched input Value 0 = SRC8 1 = ITP 46 NC NC Not Connected 47 VDDCPU_IO PWR Power supply for CPU outputs. 1.05 to 3.3V +/-5%. 48 CPUC1_F OUT Complement clock of low power differenatial CPU clock pair. This clock will be free-running during iAMT. 49 CPUT1_F OUT True clock of low power differential CPU clock pair. This clock will be free-running during iAMT. 50 GNDCPU PWR Ground Pin for CPU Outputs 51 CPUC0 OUT Complement clock of low power differential CPU clock pair. 52 CPUT0 OUT True clock of low power differential CPU clock pair. 53 VDDCPU PWR Power Supply 3.3V nominal. 54 CK_PWRGD/PD# IN Notifies CK505 to sample latched inputs, or iAMT entry/exit, or PWRDWN# mode 55 FSLB/TEST_MODE IN 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode while in test mode. Refer to Test Clarification Table. 56 GNDREF PWR Ground pin for crystal oscillator circuit |
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