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9LPRS436CGILF Datasheet(PDF) 10 Page - Integrated Device Technology |
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9LPRS436CGILF Datasheet(HTML) 10 Page - Integrated Device Technology |
10 / 20 page IDT® Low Power Clock for Intel Atom®-Based Systems 1561C — 08/24/11 9LPRS436C Low Power Clock for Intel Atom ®-Based Systems 10 Electrical Characteristics - USB48MHz, 12/48MHz PARAMETER SYMBOL CON DITIONS MIN TYP MAX UNITS NOTES Long Accuracy ppm see Tperiod min-max values -100 100 ppm1,2 Clock period Tperiod 48.00MHz output nominal 20.83125 20.83542 ns 2,3 Absolute min/max period Tabs 48.00MHz output nominal 20.48125 21.18542 ns 2 Output High Voltage VOH IOH = -1 mA 2.4 V 1 Output Low Voltage VOL IOL = 1 mA 0.4 V 1 Rising Edge Slew Rate (USB48M) tSLR Measured from 0.8 to 2.0 V 1 1.7 2 V/ns 1 Falling Edge Slew Rate (USB48M) tFLR Measured from 2.0 to 0.8 V 1 1.7 2 V/ns 1 Rising Edge Slew Rate (12/48M) tSLR Measured from 0.8 to 2.0 V 1 1.7 2 V/ns 1 Falling Edge Slew Rate (12/48M) tFLR Measured from 2.0 to 0.8 V 1 1.7 2 V/ns 1 Duty Cycle dt1 VT = 1.5 V 45 50.6 55 % 1 Jitter, Cycle to cycle tjcyc-cyc VT = 1.5 V 150 350 ps 1 Electrical Characteristics - 25MHz PARAMETER SYMBOL CON DITIONS MIN TYP MAX UNITS NOTES Long Accuracy ppm see Tperiod min-max values -100 0 100 ppm1,2 Clock period Tperiod 25.00MHz output nominal 39.99600 40.00400 ns 2,3 Absolute min/max period T abs 25.00MHz output nominal 39.32360 40.67640 ns 2 Output High Voltage V OH I OH = -1 mA 2.4 V 1 Output Low Voltage VOL IOL = 1 mA 0.4 V 1 Rising Edge Slew Rate t SLR Measured from 0.8 to 2.0 V 1 1.8 2 V/ns 1 Falling Edge Slew Rate tFLR Measured from 2.0 to 0.8 V 1 1.8 2 V/ns 1 Duty Cycle d t1 V T = 1. 5 V 45 49.6 55 %1 Jitter, Cycle to cycle t jcyc-cyc V T = 1. 5 V 150 500 ps 1 Electrical Characteristics - 12.288MHz PARAMETER SYMBOL CON DITIONS MIN TYP MAX UNITS NOTES Long Accuracy ppm see Tperiod min-max values -100 0 100 ppm1,2 Clock period Tperiod 12.288MHz output nominal 81.37207 81.38835 ns 2,3 Absolute min/max period T abs 12.288MHz output nominal 80.87207 81.88835 ns 2 Output High Voltage V OH I OH = -1 mA 2.4 V 1 Output Low Voltage VOL IOL = 1 mA 0.4 V 1 Rising Edge Slew Rate t SLR Measured from 0.8 to 2.0 V 1 1.8 2 V/ns 1 Falling Edge Slew Rate tFLR Measured from 2.0 to 0.8 V 1 1.8 2 V/ns 1 Duty Cycle d t1 V T = 1. 5 V 45 50.1 55 %1 Jitter, Cycle to cycle t jcyc-cyc V T = 1. 5 V 133 500 ps 1 Electrical Characteristics - REF-14.318MHz PARAMETER SYMBOL C OND ITIONS MIN TYP MAX UNITS Notes Long Accuracy ppm see Tperiod min-max va lues -10 0 0 100 ppm 1,2 Clock period Tperiod 14.3 18MH z output nominal 69 .82033 69.8 6224 ns 2,3 Absolute min/max period Tabs 14.3 18MH z output nominal 69 .83400 70.8 4800 ns 2 Output High Voltage VOH IOH = -1 mA 2.4 V 1 Output Low Voltage VOL IOL = 1 mA 0 .4 V 1 Rising Edge Slew Rate tSLR Measure d from 0.8 to 2.0 V 1 1.5 4 V/ns 1 Falling Edge Slew Rate tFL R Measure d from 2 .0 to 0.8 V 1 1.4 4 V/ns 1 Duty Cycle dt1 VT = 1.5 V 45 50.2 55 % 1 Jitter, Cycle to cycle tjcyc-cyc VT = 1.5 V 13 9 1000 ps1 *T A = Tambient; VDD = 3.3 V +/-5%; C L=5pF, Rs= 22Ω (unles s specif ied otherwise) 1 Guaranteed by design and characterization, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz 3 The average period over any 1us period of time Electrical Characteristics - Phase Jitter PARAMETER SYMBOL CONDITIONS MIN TYP. MAX UNITS NOTES tjphPCIe1 PCIe Gen 1 REFCLK phase jitter 30 86 ps 1,2,3 t jph PCIe2L o PCIe Gen 2 REFCLK phase jitter Lo-band content 1.3 3 ps (RMS) 1,2,3 t jphPC Ie2Hi PCIe Gen 2 REFCLK phase jitter Hi-band content 1.7 3.1 ps (RMS) 1,2,3 *T A = Tambient ; VDD = 3. 3 V +/-5%; C L=5pF, R s= 22Ω (unles s specif ied otherwis e) Notes on Phase Jitter: 2 Device driven by 932S421BGLF or equivalent 2 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a B ER of 1-12 3 Applies to PCIEX(3:0) outputs only. 1 See http://www.pcisig.com for complete specs. Guaranteed by design and characterization, not tested in production. Jitter, Phase |
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