ICS845252AKI REVISION A SEPTEMBER 30, 2009

3

©2009 Integrated Device Technology, Inc.

ICS845252I Data Sheet

FEMTOCLOCK™ CRYSTAL-TO-CML CLOCK GENERATOR

Function Tables

Table 3A. PLL Reference Clock Select Function Table

NOTE: REF_SEL is an asynchronous control.

Table 3B. PLL Feedback Select Function Table

NOTE: FBSEL is an asynchronous control.

Table 3C. Output Divider Select Function Table

NOTE: FSEL[1:0] are asynchronous controls.

Table 3D. PLL nBYPASS Function Table

NOTE: nBYPASS is an asynchronous control.

Table 3E. Output Enable Function Table

NOTE: nOE is an asynchronous control.

Input

Operation

REF_SEL

0 (default)

The crystal interface is the selected.

1

The REF_CLK input is the selected.

Input

Operation

FBSEL

0 (default)

Input

Operation

FSEL1

FSEL0

FBSEL = 0

FBSEL = 1

0 (default)

0 (default)

312.5MHz

250MHz

01

156.25MHz

125MHz

10

125MHz

100MHz

11

62.5MHz

50MHz

Input

Operation

nBYPASS

0

output divider. AC specifications do not apply in PLL bypass mode.

1 (default)

feedback divider and then divided by the selected output divider.

Input

Operation

nOE

0 (default)

Outputs enabled.

1

Outputs disabled (high-impedance).