ICS840272AGI REVISION A JULY 26, 2010

2

©2010 Integrated Device Technology, Inc.

ICS840272I Data Sheet

SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR

Table 1. Pin Descriptions

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Table 2. Pin Characteristics

Number

Name

Type

Description

Power

Core supply pin.

2

LOCK_DT

Output

Lock detect. Logic HIGH when PLL is locked.

3

REF_SEL

Input

Pulldown

Selects the input reference clock. When LOW, selects CLK0, nCLK0.

When HIGH, selects CLK1, nCLK1. LVCMOS/LVTTL interface levels.

4

SEL0

Input

Pullup

Selects the input reference frequency and the PLL bypass mode. See Table 3A.

LVCMOS/LVTTL interface levels.

5

SEL1

Input

Pulldown

Selects the input reference frequency and the PLL bypass mode. See Table 3A.

LVCMOS/LVTTL interface levels.

6

OE

Input

Pulldown

8kHz output enable pin. When LOW, QB is disabled. When HIGH, QB is enabled.

LVCMOS/LVTTL interface levels. See Table 3B.

Power

Analog supply pin.

8, 13

GND

Power

Power supply ground.

9

nCLK1

Input

Pullup/

Pulldown

10

CLK1

Input

Pulldown

Non-inverting differential clock input.

11

nCLK0

Input

Pullup/

Pulldown

12

CLK0

Input

Pulldown

Non-inverting differential clock input.

14

QB

Output

Single-ended clock output. LVCMOS/LVTTL interface levels.

15

QA

Output

Single-ended clock output. LVCMOS/LVTTL interface levels.

16

Power

Output supply pin.

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

Input Capacitance

4pF

Input Pullup Resistor

51

k

Ω

Input Pulldown Resistor

51

k

Ω

Output Impedance

17

Ω