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ICS840272I Datasheet(PDF) 1 Page - Integrated Device Technology |
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ICS840272I Datasheet(HTML) 1 Page - Integrated Device Technology |
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1 / 15 page  DATA SHEET ICS840272AGI REVISION A JULY 26, 2010 1 ©2010 Integrated Device Technology, Inc. Synchronous Ethernet Frequency Translator ICS840272I General Description The ICS840272I is a PLL-based Frequency Translator intended for use in Synchronous Ethernet applications. This high performance device is optimized to generate 25MHz and 8kHz LVCMOS clock outputs. The ICS840272I accepts the following differential or single-ended input signals: 161.1328125MHz (10GbE Mode), 156.25MHz (1GbE Mode), or 125MHz (Recovered clock from 10/100/1000BaseT Ethernet PHY). The extended temperature range supports telecommunication and networking end equipment requirements. Features • Two single-ended outputs (LVCMOS or LVTTL levels), output impedance: 17 Ω • Single-ended lock detect output (LVCMOS or LVTTL levels) • Two selectable differential clock inputs • Differential input pair (CLKx, nCLKx) accepts LVPECL, LVDS, LVHSTL, SSTL, HCSL input levels • Internal resistor bias on nCLK pin allows the user to drive CLK input with external single-ended (LVCMOS/ LVTTL) input levels • Selectable input frequencies: 161.1328MHz, 156.25MHz or 125MHz • Output frequency: 25MHz, 8kHz • Full 3.3V supply voltage • -40°C to 85°C ambient operating temperature • Available in lead-free (RoHS 6) package 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 GND VDDA OE SEL1 SEL0 REF_SEL LOCK_DT VDD VDDO QA QB GND CLK0 nCLK0 CLK1 nCLK1 Input Control 00 = PLL Bypass, 25MHz Input 01 = 161.1328125MHz (default) 10 = 156.25MHz 11 = 125MHz M QA LOCK_DT 25MHz 8kHz QB CLK0 nCLK0 Pullup/Pulldown Pulldown CLK1 nCLK1 REF_SEL 0 1 P N PLL 0 1 ÷3125 Pullup/Pulldown Pulldown Pulldown SEL[1:0] Pulldown:Pullup OE Pulldown ICS840272I 16 Lead TSSOP 4.40mm x 5.0mm x 0.925mm package body G Package Top View Pin Assignment Block Diagram |
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