8624BYIT datasheet(1/16 Pages) IDT

Part #	8624BYIT

Description	LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER

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Manufacturer	IDT [Integrated Device Technology]

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8624BYI

www.idt.com

REV. C JULY 30, 2010

1

ICS8624I

LOW SKEW, 1-TO-5

DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER

GENERAL DESCRIPTION

The

ICS8624I

is

a

high

performance,

1-to-5

Differential-to-HSTL zero delay buffer. The ICS8624I

has two selectable clock input pairs. The CLK0,

nCLK0 and CLK1, nCLK1 pair can accept most standard

differential input levels. The VCO operates at a frequency

range of 250MHz to 630MHz. Utilizing one of the outputs

as feedback to the PLL, output frequencies up to 630MHz

can be regenerated with zero delay with respect to the

input. Dual reference clock inputs support reduntant clock

or multiple reference applications..

BLOCK DIAGRAM

PIN ASSIGNMENT

FEATURES

• Fully integrated PLL

• Five differential HSTL compatible outputs

• Selectable differential CLKx, nCLKx input pairs

• CLKx, nCLKx pairs can accept the following differential

input levels: LVPECL, LVDS, HSTL, SSTL, HCSL

• Output frequency range: 31.25MHz to 630MHz

• Input frequency range: 31.25MHz to 630MHz

• VCO range: 250MHz to 630MHz

• External feedback for “zero delay” clock regeneration

• Cycle-to-cycle jitter: 35ps (maximum)

• Output skew: 50ps (maximum)

• Static phase offset: 30ps ±125ps

• 3.3V core, 1.8V output operating supply

• -40°C to 85°C ambient operating temperature

• Available in both standard and lead-free RoHS-compliant

packages

32 31 30 29 28 27 26 25

9

10 11 12 13 14 15 16

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

VDDO

Q3

nQ3

Q2

nQ2

Q1

nQ1

VDDO

SEL0

SEL1

CLK0

nCLK0

CLK1

nCLK1

CLK_SEL

MR

32-Lead LQFP

7mm x 7mm x 1.4mm body package

Y Package

Top View

ICS8624I

PLL_SEL

CLK0

nCLK0

CLK1

nCLK1

CLK_SEL

FB_IN

nFB_IN

SEL0

SEL1

MR

Q0

nQ0

Q1

nQ1

Q2

nQ2

Q3

nQ3

Q4

nQ4

0

1

PLL

0

1

÷4, ÷8

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