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872S480BKLF Datasheet(PDF) 7 Page - Integrated Device Technology |
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872S480BKLF Datasheet(HTML) 7 Page - Integrated Device Technology |
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7 / 20 page  ICS872S480BK REVISION A APRIL 19, 2011 7 ©2011 Integrated Device Technology, Inc. ICS872S480 Data Sheet DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR Parameter Measurement Information 3.3V Output Load AC Test Circuit Cycle-to-Cycle Jitter Static Phase Offset Differential Input Level Output Skew Output Duty Cycle/Pulse Width/Period SCOPE HSTL Qx nQx GND 0V VDDA 3.3V ± 5% 3.3V ± 5% VDD nQ[0:1] Q[0:1] ➤ ➤ tcycle n tcycle n+1 tjit(cc) = |tcycle n – tcycle n+1| 1000 Cycles nCLK[0:1] CLK[0:1] nFB_IN FB_IN ➤ t(Ø) t(Ø)mean = Static Phase Offset (where t(Ø) is any random sample, and t(Ø)mean is the average of the sampled cycles measured on controlled edges) nCLK0, nCLK1 CLK0, CLK1 VDD GND V CMR Cross Points V PP nQx Qx nQy Qy tsk(o) t PW t PERIOD t PW t PERIOD odc = x 100% nQ[0:1] Q[0:1] |
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