ICS872S480BK REVISION A APRIL 19, 2011

3

©2011 Integrated Device Technology, Inc.

ICS872S480 Data Sheet

DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR

Table 1. Pin Descriptions

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Table 2. Pin Characteristics

Number

Name

Type

Description

1

CLK0

Input

Pulldown

Non-inverting differential clock input.

2

nCLK0

Input

Pullup

Inverting differential clock input.

3, 20, 28

GND

Power

Power supply ground.

4

CLK1

Input

Pulldown

Non-inverting differential clock input.

5

nCLK1

Input

Pullup

Inverting differential clock input.

6

PLL_BYPASS

Input

Pulldown

PLL bypass pin. When HIGH, the PLL is bypassed and the reference clock is

passed directly to the output dividers. LVCMOS/LVTTL interface levels.

7

FB_IN

Input

Pulldown

Non-inverting differential external feedback input.

8

nFB_IN

Input

Pullup

Inverting differential external feedback input.

9, 10

nQFB, QFB

Output

Differential feedback output pair. HSTL interface levels. See Table 4D.

11, 16, 24,

25, 32

Power

Core supply pins.

12, 13

nQ1, Q1

Output

Differential output pair. HSTL interface levels.

14, 15

nQ0, Q0

Output

Differential output pair. HSTL interface levels.

17

Power

Analog supply pin.

18

OE

Input

Pullup

Output enable pin. LVCMOS/LVTTL interface levels.

19

FREQ_SEL

Input

Pullup

Frequency select pin. LVCMOS/LVTTL interface levels.

21

CLK_IND

Output

Clock indicator pin. When LOW, CLK0, nCLK0 is selected. When HIGH, CLK1,

nCLK1 is selected.

22

LOR1

Output

Loss of Reference Indicator for CLK1, nCLK1. LVCMOS/LVTTL interface levels.

23

LOR0

Output

Loss of Reference Indicator for CLK0, nCLK0. LVCMOS/LVTTL interface levels.

26

VOUT_SEL

Input

Pulldown

Output voltage select pin. LVCMOS/LVTTL interface levels.

27, 29

nc

Unused

No connect.

30

AUTO_SEL

Input

Pullup

Dynamic Clock switch enable pin. When LOW, disables internal Dynamic Clock

Switch circuitry and CLK_INDICATOR will track REF_SEL. When HIGH, Dynamic

Clock Switch is enabled. LVCMOS/LVTTL interface levels.

31

REF_SEL

Input

Pulldown

Reference clock select pin. When LOW selects CLK0, nCLK0, when HIGH selects

CLK1, nCLK1. LVCMOS/LVTTL interface levels.

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

Input Capacitance

2pF

Input Pullup Resistor

51

k

Ω

Input Pulldown Resistor

51

k

Ω