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849N202CKI-DDDLFT Datasheet(PDF) 8 Page - Integrated Device Technology |
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849N202CKI-DDDLFT Datasheet(HTML) 8 Page - Integrated Device Technology |
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8 / 39 page  ICS849N202CKI REVISION A SEPTEMBER 26, 2011 8 ©2011 Integrated Device Technology, Inc. ICS849N202I Data Sheet FemtoClock® NG Universal Frequency Translator Holdover / Free-run Behavior When both input references have failed (Automatic mode) or the selected input has failed (Manual mode), the ICS849N202I will enter holdover (Low Bandwidth Frequency Translator mode) or free-run (High Bandwidth Frequency Translator mode) state . In both cases, once the input reference is lost, the PLL will stop making adjustments to the output phase. If operating in Low Bandwidth Frequency Translation mode, the PLL will continue to reference itself to the local oscillator and will hold its output phase and frequency in relation to that source. Output stability is determined by the stability of the local oscillator in this case. However, if operating in High Bandwidth Frequency Translation mode, the PLL no longer has any frequency reference to use and output stability is now determined by the stability of the internal VCO. If the device is programmed to perform Manual switching, once the selected input reference recovers, the ICS849N202I will switch back to that input reference. If programmed for either Automatic mode, the device will switch back to whichever input reference has a valid clock first. The switchover that results from returning from holdover or free-run is handled in the same way as a switch between two valid input references as described in the previous section. Output Configuration The two outputs of the ICS849N202I both provide the same clock frequency. Both must operate from the same output voltage level of 3.3V or 2.5V, although this output voltage may be less than or equal to the core voltage (3.3V or 2.5V) the rest of the device is operating from. The output voltage level used on the two outputs is supplied on the VCCO pin. The two outputs are individually selectable as LVDS or LVPECL output types via the Q0_TYPE and Q1_TYPE register bits. These two selection bits are provided in each configuration to allow different output type settings under each configuration. The two outputs can be enabled individually also via both register control bits and input pins. When both the OEn register bit and OEn pin are enabled, then the appropriate output is enabled. The OEn register bits default to enabled so that by default the outputs can be directly controlled by the input pins. Similarly, the input pins are provisioned with weak pull-ups so that if they are left unconnected, the output state can be directly controlled by the register bits. When the differential output is in the disabled state, it will show a high impedance condition. Serial Interface Configuration Description The ICS849N202I has an I2C-compatible configuration interface to access any of the internal registers (Table 4D) for frequency and PLL parameter programming. The ICS849N202I acts as a slave device on the I2C bus and has the address 0b11011xx, where xx is set by the values on the S_A0 & S_A1 pins (see Table 4A for details). The interface accepts byte-oriented block write and block read operations. An address byte (P) specifies the register address (Table 4D) as the byte position of the first register to write or read. Data bytes (registers) are accessed in sequential order from the lowest to the highest byte (most significant bit first, see table 4B, 4C). Read and write block transfers can be stopped after any complete byte transfer. It is recommended to terminate I2C the read or write transfer after accessing byte #23. For full electrical I2C compliance, it is recommended to use external pull-up resistors for SDATA and SCLK. The internal pull-up resistors have a size of 50k Ω typical. Note: if a different device slave address is desired, please contact IDT. Table 4A. I2C Device Slave Address Table 4B. Block Write Operation Table 4C. Block Read Operation 1101 1 S_A1 S_A0 R/W Bit 1 2:8 9 10 11:18 19 20:27 28 29-36 37 ... ... ... Description START Slave Address W (0) ACK Address Byte (P) ACK Data Byte (P) ACK Data Byte (P+1) ACK Data Byte ... ACK STOP Length (bits) 17 1 1 8 1 8 1 8 1 8 1 1 Bit 1 2:8 9 10 11:18 19 20 21:27 28 29 30:37 38 39-46 47 ... ... ... Description START Slave Address W (0) A C K Address Byte (P) A C K Repeate d START Slave Address R (1) A C K Data Byte (P) A C K Data Byte (P+1) A C K Data Byte ... A C KSTOP Length (bits) 17 1 1 8 1 1 7 1 1 8 1 8 1 8 1 1 |
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