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849N202CKI-DDDLF Datasheet(PDF) 9 Page - Integrated Device Technology |
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849N202CKI-DDDLF Datasheet(HTML) 9 Page - Integrated Device Technology |
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9 / 39 page  ICS849N202CKI REVISION A SEPTEMBER 26, 2011 9 ©2011 Integrated Device Technology, Inc. ICS849N202I Data Sheet FemtoClock® NG Universal Frequency Translator Register Descriptions Please consult IDT for configuration software and/or programming guides to assist in selection of optimal register settings for the desired configurations. Table 4D. I2C Register Map Register Bit Color Key Reg Binary Register Address Register Bit D7 D6 D5 D4 D3 D2 D1 D0 0 00000 MFRAC0[17] MFRAC0[16] MFRAC0[15] MFRAC0[14] MFRAC0[13] MFRAC0[12] MFRAC0[11] MFRAC0[10] 1 00001 MFRAC1[17] MFRAC1[16] MFRAC1[15] MFRAC1[14] MFRAC1[13] MFRAC1[12] MFRAC1[11] MFRAC1[10] 2 00010 MFRAC0[9] MFRAC0[8] MFRAC0[7] MFRAC0[6] MFRAC0[5] MFRAC0[4] MFRAC0[3] MFRAC0[2] 3 00011 MFRAC1[9] MFRAC1[8] MFRAC1[7] MFRAC1[6] MFRAC1[5] MFRAC1[4] MFRAC1[3] MFRAC1[2] 4 00100 MFRAC0[1] MFRAC0[0] MINT0[7] MINT0[6] MINT0[5] MINT0[4] MINT0[3] MINT0[2] 5 00101 MFRAC1[1] MFRAC1[0] MINT1[7] MINT1[6] MINT1[5] MINT1[4] MINT1[3] MINT1[2] 6 00110 MINT0[1] MINT0[0] P0[16] P0[15] P0[14] P0[13] P0[12] P0[11] 7 00111 MINT1[1] MINT1[0] P1[16] P1[15] P1[14] P1[13] P1[12] P1[11] 8 01000 P0[10] P0[9] P0[8] P0[7] P0[6] P0[5] P0[4] P0[3] 9 01001 P1[10] P1[9] P1[8] P1[7] P1[6] P1[5] P1[4] P1[3] 10 01010 P0[2] P0[1] P0[0] M1_0[16] M1_0[15] M1_0[14] M1_0[13] M1_0[12] 11 01011 P1[2] P1[1] P1[0] M1_1[16] M1_1[15] M1_1[14] M1_1[13] M1_1[12] 12 01100 M1_0[11] M1_0[10] M1_0[9] M1_0[8] M1_0[7] M1_0[6] M1_0[5] M1_0[4] 13 01101 M1_1[11] M1_1[10] M1_1[9] M1_1[8] M1_1[7] M1_1[6] M1_1[5] M1_1[4] 14 01110 M1_0[3] M1_0[2] M1_0[1] M1_0[0] N0[10] N0[9] N0[8] N0[7] 15 01111 M1_1[3] M1_1[2] M1_1[1] M1_1[0] N1[10] N1[9] N1[8] N1[7] 16 10000 N0[6] N0[5] N0[4] N0[3] N0[2] N0[1] N0[0] BW0[6] 17 10001 N1[6] N1[5] N1[4] N1[3] N1[2] N1[1] N1[0] BW1[6] 18 10010 BW0[5] BW0[4] BW0[3] BW0[2] BW0[1] BW0[0] Q1_TYPE0 Q0_TYPE0 19 10011 BW1[5] BW1[4] BW1[3] BW1[2] BW1[1] BW1[0] Q1_TYPE1 Q0_TYPE1 20 10100 MODE_SEL[1] MODE_SEL[0] CONFIG CFG_PIN_REG OE1 OE0 Rsvd Rsvd 21 10101 CLK_SEL AUTO_MAN[1] AUTO_MAN[0] 0 ADC_RATE[1] ADC_RATE[0] LCK_WIN[1] LCK_WIN[0] 22 10110 10 1 0 0 0 0 0 23 10111 CLK_ACTIVE HOLDOVER CLK1BAD CLK0BAD XTAL_BAD LOCK_IND Rsvd Rsvd Configuration 0 Specific Bits Configuration 1 Specific Bits Global Control & Status Bits |
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