2308-2DCG datasheet(2/13 Pages) IDT

Part #	2308-2DCG

Description	3.3V ZERO DELAY CLOCK MULTIPLIER

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Manufacturer	IDT [Integrated Device Technology]

Direct Link	http://www.idt.com

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COMMERCIALANDINDUSTRIALTEMPERATURERANGES

IDT2308

3.3V ZERO DELAY CLOCK MULTIPLIER

PIN CONFIGURATION

SOIC/ TSSOP

TOP VIEW

REF

CLKA1

S2

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

1

CLKA2

GND

CLKB1

FBK

CLKA4

GND

S1

VDD

CLKB2

CLKB3

CLKB4

CLKA3

Symbol

Rating

Max.

Unit

VDD

SupplyVoltageRange

–0.5 to +4.6

V

VI(2)

InputVoltageRange(REF)

–0.5 to +5.5

V

VI

InputVoltageRange

–0.5to

V

(except REF)

VDD+0.5

IIK (VI < 0)

InputClampCurrent

–50

mA

IOK

TerminalVoltagewithRespect

±50

mA

(VO < 0 or VO > VDD) to GND (inputs VIH 2.5, VIL 2.5)

IO

ContinuousOutputCurrent

±50

mA

(VO = 0 to VDD)

VDD or GND

ContinuousCurrent

±100

mA

TA = 55°C

Maximum Power Dissipation

0.7

W

(instillair)(3)

TSTG

StorageTemperatureRange

–65to+150

°C

Operating

CommercialTemperature

0 to +70

°C

Temperature

Range

Operating

IndustrialTemperature

-40 to +85

°C

Temperature

Range

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may

cause permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those indicated in the

operational sections of this specification is not implied. Exposure to absolute maximum

rating conditions for extended periods may affect reliability.

2. The input and output negative-voltage ratings may be exceeded if the input and output

clamp-current ratings are observed.

3. The maximum package power dissipation is calculated using a junction temperature

of 150

°C and a board trace length of 750 mils.

APPLICATIONS:

• SDRAM

• Telecom

• Datacom

• PC Motherboards/Workstations

• Critical Path Delay Designs

Pin Number

FunctionalDescription

REF (1)

1

InputReferenceClock,5VoltTolerantInput

CLKA1(2)

2

Clock Output for Bank A

CLKA2(2)

3

Clock Output for Bank A

VDD

4

3.3V Supply

GND

5

Ground

CLKB1(2)

6

Clock Output for Bank B

CLKB2(2)

7

Clock Output for Bank B

S2(3)

8

Select Input, Bit 2

S1(3)

9

Select Input, Bit 1

CLKB3(2)

10

Clock Output for Bank B

CLKB4(2)

11

Clock Output for Bank B

GND

12

Ground

VDD

13

3.3V Supply

CLKA3(2)

14

Clock Output for Bank A

CLKA4(2)

15

Clock Output for Bank A

FBK

16

PLLFeedbackInput

NOTES:

1. Weak pull down.

2. Weak pull down on all outputs.

3. Weak pull ups on these inputs.

PIN DESCRIPTION

ABSOLUTE MAXIMUM RATINGS(1)

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