Electronic Components Datasheet Search |
|
1339-2DCGI8 Datasheet(PDF) 9 Page - Integrated Device Technology |
|
1339-2DCGI8 Datasheet(HTML) 9 Page - Integrated Device Technology |
9 / 27 page IDT1339 REAL-TIME CLOCK WITH SERIAL I2C INTERFACE RTC IDT® REAL-TIME CLOCK WITH SERIAL I2C INTERFACE 9 IDT1339 REV K 032910 Table 5. SQW/INT Output Bit 2: Interrupt Control (INTCN). This bit controls the relationship between the two alarms and the interrupt output pins. When the INTCN bit is set to logic 1, a match between the timekeeping registers and the alarm 1 or alarm 2 registers activate the SQW/INT pin (provided that the alarm is enabled). When the INTCN bit is set to logic 0, a square wave is output on the SQW/INT pin. This bit is set to logic 0 when power is first applied. Bit 1: Alarm 2 Interrupt Enable (A2IE). When set to a logic 1, this bit permits the Alarm 2 Flag (A2F) bit in the status register to assert SQW/INT (when INTCN = 1). When the A2IE bit is set to logic 0 or INTCN is set to logic 0, the A2F bit does not initiate an interrupt signal. The A2IE bit is disabled (logic 0) when power is first applied. Bit 0: Alarm 1 Interrupt Enable (A1IE). When set to logic 1, this bit permits the Alarm 1 Flag (A1F) bit in the status register to assert SQW/INT (when INTCN = 1). When the A1IE bit is set to logic 0 or INTCN is set to logic 0, the A1F bit does not initiate an interrupt signal. The A1IE bit is disabled (logic 0) when power is first applied. Status Register (0Fh) Bit 7: Oscillator Stop Flag (OSF). A logic 1 in this bit indicates that the oscillator either is stopped or was stopped for some period of time and may be used to judge the validity of the clock and date data. This bit is edge triggered and is set to logic 1 when the oscillator stops. The following are examples of conditions that can cause the OSF bit to be set: 1) The first time power is applied. 2) The voltage on both VCC and VBACKUP are insufficient to support oscillation. 3) The EOSC bit is turned off. 4) External influences on the crystal (e.g., noise, leakage, etc.). This bit remains at logic 1 until written to logic 0. This bit can only be written to a logic 0. Bit 1: Alarm 2 Flag (A2F). A logic 1 in the Alarm 2 Flag bit indicates that the time matched the alarm 2 registers. If the A2IE bit is a logic 1 and the INTCN bit is set to a logic 1, the SQW/INT pin is also asserted. A2F is cleared when written to logic 0. This bit can only be written to logic 0. Attempting to write to logic 1 leaves the value unchanged. Bit 0: Alarm 1 Flag (A1F). A logic 1 in the Alarm 1 Flag bit indicates that the time matched the alarm 1 registers. If the A1IE bit is a logic 1 and the INTCN bit is set to a logic 1, the SQW/INT pin is also asserted. A1F is cleared when written to logic 0. This bit can only be written to logic 0. Attempting to write to logic 1 leaves the value unchanged. INTCN RS2 RS1 SQW/INT Output A2IE A1IE 0 0 0 1 Hz X X 0 0 1 4.096 kHz X X 0 1 0 8.192 kHz X X 0 1 1 32.768 kHz X X 1 X X A1F 0 1 1 X X A2F 1 0 1 X X A2F + A1F 1 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OSF 0 0 0 0 0 A2F A1F |
Similar Part No. - 1339-2DCGI8 |
|
Similar Description - 1339-2DCGI8 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |