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IDT72V70200 3.3V TIME SLOT INTERCHANGE

TABLE 6 — INTER.ACE MODE SELECTION (IMS) REGISTER BITS

TABLE 5 — CONTROL REGISTER (CR) BITS

Read/Write Address:

Reset Value:

15

14

13

12

11

10

9876543210

0000000000

MBP

MS

STA3

STA2

STA1

STA0

Bit

Name

Description

15-6

Unused

Must be zero for normal operation.

5

MBP

When 1, the connection memory block programming feature is ready for the programming of Connection

(Memory Block Program)

Memory high bits, bit 11 to bit 15. When 0, this feature is disabled.

4

MS

When 0, connection memory is selected for read or write operations. When 1, the data memory is selected

(Memory Select)

for read operations and connection memory is selected for write operations.

(No microprocessor write operation is allowed for the data memory.)

3-0

STA3-0

The binary value expressed by these bits refers to the input or output data stream, which corresponds

(Stream Address Bits)

to the subsection of memory made accessible for subsequent operations. (STA3 = MSB, STA0 = LSB)

Read/Write Address:

Reset Value:

Bit

Name

Description

15-10

Unused

Must be zero for normal operation.

9-5

BPD4-0

These bits carry the value to be loaded into the connection memory block whenever the memory block

(Block Programming Data)

programming feature is activated. After the MBP bit in the control register is set to 1 and the BPE bit is

set to 1, the contents of the bits BPD4-0 are loaded into bit 15 to 11 of the connection memory. Bit 10 to

bit 0 of the connection memory are set to 0.

4

BPE

A zero to one transition of this bit enables the memory block programming function. The BPE and

(Begin Block Programming

BPD4-0 bits in the IMS register have to be defined in the same write operation. Once the BPE bit is set

Enable)

HIGH, the device requires two frames to complete the block programming. After the programming function

has finished, the BPE bit returns to zero to indicate the operation is completed. When the BPE = 1, the BPE

or MBP can be set to 0 to ensure proper operation. When BPE = 1, the other bit in the IMS register

must not be changed for two frames to ensure proper operation.

3

OSB

When ODE = 0 and OSB = 0, the output drivers of TX0 to TX15 are in high impedance mode. When

(Output Stand By)

ODE= 0 and OSB = 1, the output driver of TX0 to TX15 function normally. When ODE = 1, TX0 to TX15

output drivers function normally.

2

SFE

A zero to one transition in this bit starts the frame evaluation procedure. When the CFE bit in the FAR

(Start Frame Evaluation)

register changes from zero to one, the evaluation procedure stops. To start another fame evaluation

cycle, set this bit to zero for at least one frame.

1-0

Unused

Must be zero for normal operation.

15

14

13

12

11

10

9876543210

000000

BPD4 BPD3 BPD2 BPD1 BPD0

BPE

OSB

SFE

0

0

9