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5P49EE802NDGI8 Datasheet(PDF) 7 Page - Integrated Device Technology |
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5P49EE802NDGI8 Datasheet(HTML) 7 Page - Integrated Device Technology |
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7 / 25 page  IDT5P49EE802 VERSACLOCK® LOW POWER CLOCK GENERATOR EEPROM CLOCK GENERATOR IDT™ VERSACLOCK® LOW POWER CLOCK GENERATOR 7 IDT5P49EE802 REV C 061810 VSYNC, HSYNC, DOT_CLK – Modulation Rate Relationship LOOP FILTER The loop filter for each PLL can be programmed to optimize the jitter performance. The low-pass frequency response of the PLL is the mechanism that dictates the jitter transfer characteristics. The loop bandwidth can be extracted from the jitter transfer. A narrow loop bandwidth is good for jitter attenuation while a wide loop bandwidth is best for low jitter generation. The specific loop filter components that can be programmed are the resistor via the RZ[4:0] bits, zero capacitor via the CZ[2:0] bits, pole capacitor via the CP[1:0] bits, and the charge pump current via the IP#[2:0] bits. The following equations govern how the loop filter is set: Zero capacitor (Cz) = 280pF Pole capacitor (Cp) = 30pF Charge pump (Ip) = IP#[2:0] uA VCO gain (KVCO) = 350MHz/V * 2 Integer multiple of HSYNC periods VSYNC HSYNC DOT_CLK Modulation Rate X/2 X X/2 X X = Number of cycles of DOT_CLK per HSYNC period. X/2 = Number of cycles of DOT_CLK that the modulation edge rises/falls. |
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