IDT5P49EE801

EEPROM CLOCK GENERATOR

4

IDT5P49EE801 REV C 061810

Note 1: Outputs are user programmable to drive single-ended 1.8V/2.5V/3.3V LVTTL. Alway completely power up VDD and

VDDx prior to applying VDDO power. Always power up device into “Active” configuration modes, prior to asserting Power

Down/Sleep mode SEL=00.

Note 2: Default configuration CLK4=Buffered MHz Reference output and CLK2=Buffered 32.768kHz output. All other

outputs are off.

OUT2

13

O

Adjustable

Configurable clock output 2. Single-ended output voltage levels

are register controlled by either VDDO1, VDDO2 or VDDO3.

SEL1

14

I

LVTTL

Configuration select pin. Weak internal pull down resistor.

OUT1

15

O

Adjustable

Configurable clock output 1. Single-ended output voltage levels

are register controlled by either VDDO1, VDDO2 or VDDO3.

VDD

16

Power

Device power supply. Connect to 1.8V.

VDD

17

Power

Device power supply. Connect to 1.8V.

OUT0

18

O

Adjustable

Configurable clock output 0. Single-ended output voltage levels

are register controlled by either VDDO1, VDDO2 or VDDO3.

VDDO3

19

Power

Device power supply. Connect to 1.8 to 3.3V. Using register

settings, select output voltage levels forOUT0-OUT6.

SCLK

20

I

LVTTL

OUT6B

21

O

Adjustable

Configurable clock output 6B. Output voltage level is controlled

by VDDO1.

OUT6A

22

O

Adjustable

Configurable clock output 6B. Output voltage level is controlled

by VDDO1.

SDA

23

I/O

Open Drain

VDD

24

Power

Device power supply. Connect to 1.8V.

VDD

25

Power

Device power supply. Connect to 1.8V.

GND

26

Power

Connect to Ground.

XIN/ REF

27

I

LVTTL

MHz CRYSTAL_IN -- Reference crystal input or external

reference clock input.

XOUT

28

O

LVTTL

MHz CRYSTAL_OUT -- Reference crystal feedback.

EP

--

Exposed thermal pad should be externally connected to ground.

Pin Name

Pin #

I/O

Pin Type

Pin Description