9DB102BGILFT datasheet(8/13 Pages) IDT

Part #	9DB102BGILFT

Description	Two Output Differential Buffer for PCIe Gen1 & Gen2

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Manufacturer	IDT [Integrated Device Technology]

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IDT® Two Output Differential Buffer for PCIe Gen1 & Gen2

852

REV K 04/01/10

ICS9DB102

Two Output Differential Buffer for PCIe Gen1 & Gen2

8

General SMBus serial interface information for the ICS9DB102

How to Write:

•

Controller (host) sends a start bit.

• Controller (host) sends the write address D4

(h)

• ICS clock will acknowledge

• Controller (host) sends the begining byte location = N

• ICS clock will acknowledge

• Controller (host) sends the data byte count = X

• ICS clock will acknowledge

• Controller (host) starts sending Byte N through

Byte N + X -1

• ICS clock will acknowledge each byte one at a time

• Controller (host) sends a Stop bit

How to Read:

• Controller (host) will send start bit.

• Controller (host) sends the write address D4

(h)

• ICS clock will acknowledge

• Controller (host) sends the begining byte

location = N

• ICS clock will acknowledge

• Controller (host) will send a separate start bit.

• Controller (host) sends the read address D5

(h)

• ICS clock will acknowledge

• ICS clock will send the data byte count = X

• ICS clock sends Byte N + X -1

• ICS clock sends Byte 0 through byte X (if X

(h)

was written to byte 8).

• Controller (host) will need to acknowledge each byte

• Controllor (host) will send a not acknowledge bit

• Controller (host) will send a stop bit

ICS (Slave/Receiver)

T

WR

ACK

P

Byte N + X - 1

Data Byte Count = X

Beginning Byte N

stoP bit

Index Block Write Operation

Slave Address D4(h)

Beginning Byte = N

WRite

starT bit

Controller (Host)

T

starT bit

WR

WRite

RT

Repeat starT

RD

ReaD

Beginning Byte N

Byte N + X - 1

N

Not acknowledge

P

stoP bit

ICS (Slave/Receiver)

Controller (Host)

ACK

Data Byte Count = X

ACK

Slave Address D5(h)

Index Block Read Operation

Slave Address D4(h)

Beginning Byte = N

ACK

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