ICS9FG1200D-1 datasheet(1/23 Pages) IDT

Part #	ICS9FG1200D-1

Description	Frequency Gearing Clock for CPU, PCIe Gen1, Gen2

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Manufacturer	IDT [Integrated Device Technology]

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ICS9FG1200D-1

IDT®

Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD

1138C

02/08/10

Frequency Gearing Clock for CPU, PCIe Gen1, Gen2

& FBD

DATASHEET

1

Description

ICS9FG1200D-1 follows the Intel DB1200GS Differential Buffer

Specification. This buffer provides 12 output clocks for CPU Host

Bus, PCIe Gen2, or Fully Buffered DIMM applications.The outputs

are configured with two groups. Both groups (DIF 9:0) and (DIF

11:10) can be equal to or have a gear ratio to the input clock. A

differential CPU clock from a CK410B+ main clock generator,

such as the ICS932S421, drives the ICS9FG1200D-1. The

ICS9FG1200D-1 can provide outputs up to 400MHz.

Key Specifications

•

DIF output cycle-to-cycle jitter < 50ps

•

DIF output-to-output skew < 100ps across all outputs in 1:1

mode

•

56-pin SSOP/TSSOP package

•

RoHS compliant packaging

Features/Benefits

•

Drives 2 channels of 4 FBDIMMs (total of 8 FBDIMMs)

•

Power up default is all outputs in 1:1 mode

•

DIF_(9:0) can be “gear-shifted” from the input CPU Host

Clock

•

DIF_(11:10) can be “gear-shifted” from the input CPU

Host Clock

•

Spread spectrum compatible

•

Supports output clock frequencies up to 400 MHz

•

8 Selectable SMBus addresses

•

SMBus address determines PLL or Bypass mode

Functional Block Diagram

STOP

LOGIC

CLK_IN

CLK_IN#

DIF(9:0)

CONTROL

LOGIC

HIGH_BW#

SMB_A2_PLLBYP#

SMBDAT

SMBCLK

VTT_PWRGD#/PD

SPREAD

COMPATIBLE

GEARING PLL

10

IREF

OE(9:0)#

10

SMB_A0

SMB_A1

FS_A_410

STOP

LOGIC

DIF(11:10)

2

OE#

SPREAD

COMPATIBLE

1:1 PLL

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ICS9FG1200D-1 Datasheet(PDF) 1 Page - Integrated Device Technology

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