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9FG1901HKLFT Datasheet(PDF) 10 Page - Integrated Device Technology |
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9FG1901HKLFT Datasheet(HTML) 10 Page - Integrated Device Technology |
10 / 18 page IDTTM Frequency Gearing Clock for CPU, PCIe Gen1 & FBD 1386A - 02/02/10 9FG1901H Frequency Gearing Clock for CPU, PCIe Gen1 & FBD 10 SMBusTable: Control Pin Readback Register Pin # Name Control Function Type 0 1 PWD Bit 7 R X Bit 6 X Bit 5 X Bit 4 DIF_18 Output Control RW Hi-Z Enable 1 Bit 3 DIF_17 Output Control RW Hi-Z Enable 1 Bit 2 DIF_16 Output Control RW Hi-Z Enable 1 Bit 1 DIF_15 Output Control RW Hi-Z Enable 1 Bit 0 DIF_14 Output Control RW Hi-Z Enable 1 SMBusTable: 1:1 PLL Operating Set Point Register Pin # Name Control Function Type 0 1 PWD Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 RW x Bit 1 RW 1 Bit 0 RW Latch RESERVED RESERVED RESERVED RESERVED Frequency Select C See ICS9FG1901H 1:1 PLL Programming Table Frequency Select B FS_A_410 Byte 9 - - - RESERVED Byte 8 5 Readback - FS_A_410 Readback RESERVED RESERVED Byte 9, bit 2 FSC Byte 9, bit 1 FSB Byte 9, bit 0 FS_A_410 CLK_IN (CPU FSB) MHz 1:1 DIF Outputs MHz Notes 1 0 1 100.00 100.00 3 0 0 1 133.33 133.33 3 0 1 1 166.67 166.67 1 0 1 0 200.00 200.00 3 0 0 0 266.67 266.67 3 1 0 0 333.33 333.33 3 1 0 400.00 400.00 2 1 1 1 Notes:FS_A_410 = 1 1. Powerup Default for FS_A_410 = 1 2. Powerup Default for FS_A_410 = 0 3. Setting the exact FSB frequency after Power is required to meet phase jitter specs. Reserved 9FG1901H 1:1 PLL Programming |
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