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DAC1405D750HW Datasheet(PDF) 11 Page - NXP Semiconductors |
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DAC1405D750HW Datasheet(HTML) 11 Page - NXP Semiconductors |
11 / 42 page DAC1405D750 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 4 — 7 June 2011 11 of 42 NXP Semiconductors DAC1405D750 Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating Input timing (see Figure 10) fdata data rate Dual-port mode input C - - 185 MHz tw(CLK) CLK pulse width C 40 - 60 % th(i) input hold time C 1.6 - - ns tsu(i) input set-up time C 0.8 - - ns SYNC signal td delay time fSYNC = fs / 4 C - 0.21 - ns fSYNC = fs /8 C - 0.3 - ns variation C - 0.27 - ps/ C Output timing fs sampling frequency C - - 750 Msps ts settling time to 0.5 LSB D - 20 - ns NCO frequency range fNCO NCO frequency register values 00000000h D - 0 - MHz FFFFFFFFh D - 740 - MHz fstep step frequency D - 0.172 - Hz Low-power NCO frequency range fNCO NCO frequency register values 00000000h D - 0 - MHz F8000000h D - 716.875 - MHz fstep step frequency D - 23.125 - MHz Dynamic performance SFDR spurious-free dynamic range fs = 737.28 Msps fdata = 92.16 MHz; B = fdata /2 fo = 4 MHz; 0 dBFS C - 77 - dBc fdata =184.32MHz; B= fdata /2 fo =19MHz; 0dBFS I - 74 - dBc fo =70MHz; 0dBFS C - 86 - dBc SFDRRBW restricted bandwidth spurious-free dynamic range fo =153.6MHz; 0dBFS; fdata = 184.32 MHz; fs = 737.28 Msps B = 20 MHz C - 86 - dBc B=100MHz C - 80.5 - dBc B = 20 MHz; 8-tone; 500 kHz spacing C- 76 - dBc Table 5. Characteristics …continued VDDA(1V8) =VDDD(1V8) = 1.8 V; VDDA(3V3) =VDD(IO)(3V3) = 3.3 V; AGND, DGND and GNDIO shorted together; Tamb = 40 Cto+85 C; typical values measured at Tamb =25 C; RL = 50 differential; IO(fs) = 20 mA; PLL off unless otherwise specified. Symbol Parameter Conditions Test[1] Min Typ Max Unit |
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