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W989D6CBGX6E Datasheet(PDF) 2 Page - Winbond |
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W989D6CBGX6E Datasheet(HTML) 2 Page - Winbond |
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2 / 67 page  W989D6CB / W989D2CB 512Mb Mobile LPSDR Publication Release Date: Sep, 22, 2011 - 2 - Revision A01-005 8.4 Burst Termination..............................................................................................................................26 8.5 Mode Register Operation ..................................................................................................................27 8.5.1 Burst Length field (A2~A0) ....................................................................................................................... 27 8.5.2 Addressing Mode Select (A3) .................................................................................................................. 27 8.5.3 Addressing Sequence for Sequential Mode............................................................................................. 28 8.5.4 Addressing Sequence for Interleave Mode .............................................................................................. 28 8.5.5 Addressing Sequence Example (Burst Length = 8 and Input Address is 13).......................................... 29 8.5.6 Read Cycle CAS Latency = 3................................................................................................................ 29 8.5.7 CAS Latency field (A6~A4) ................................................................................................................... 30 8.5.8 Mode Register Definition .......................................................................................................................... 30 8.6 Extended Mode Register Description................................................................................................31 8.7 Simplified State Diagram...................................................................................................................32 9. CONTROL TIMING WAVEFORMS ........................................................................................... 33 9.1 Command Input Timing.....................................................................................................................33 9.2 Read Timing......................................................................................................................................34 9.3 Control Timing of Input Data (x16) ....................................................................................................35 9.4 Control Timing of Output Data (x16) .................................................................................................36 9.5 Control Timing of Input Data (x32) ....................................................................................................37 9.6 Control Timing of Output Data (x32) .................................................................................................38 9.7 Mode register Set (MRS) Cycle ........................................................................................................39 9.8 Extended Mode register Set (EMRS) Cycle......................................................................................40 10. OPERATING TIMING EXAMPLE ............................................................................................ 41 10.1 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3).......................................................41 10.2 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto Precharge)............................42 10.3 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3).......................................................43 10.4 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto Precharge)............................44 10.5 Interleaved Bank Write (Burst Length = 8) ......................................................................................45 10.6 Interleaved Bank Write (Burst Length = 8, Auto Precharge) ...........................................................46 10.7 Page Mode Read (Burst Length = 4, CAS Latency = 3) ...............................................................47 10.8 Page Mode Read / Write (Burst Length = 8, CAS Latency = 3)....................................................48 10.9 Auto Precharge Read (Burst Length = 4, CAS Latency = 3).........................................................49 10.10 Auto Precharge Write (Burst Length = 4) ......................................................................................50 10.11 Auto Refresh Cycle .......................................................................................................................51 10.12 Self Refresh Cycle ........................................................................................................................52 10.13 Power Down Mode........................................................................................................................53 10.14 Burst Read and Single Write (Burst Length = 4, CAS Latency = 3)............................................54 10.15 Deep Power Down Mode Entry.....................................................................................................55 10.16 Deep Power Down Mode Exit .......................................................................................................56 10.17 Auto Precharge Timing (Read Cycle) ...........................................................................................57 10.18 Auto Precharge Timing (Write Cycle)............................................................................................58 10.19 Timing Chart of Read to Write Cycle.............................................................................................59 10.20 Timing Chart for Write to Read Cycle ...........................................................................................59 10.21 Timing Chart for Burst Stop Cycle (Burst Stop Command)...........................................................60 10.22 Timing Chart for Burst Stop Cycle (Precharge Command) ...........................................................60 10.23 CKE/DQM Input Timing (Write Cycle)...........................................................................................61 10.24 CKE/DQM Input Timing (Read Cycle)...........................................................................................62 11. PACKAGE DIMENSION.......................................................................................................... 63 11.1 : LPSDR X 16..................................................................................................................................63 11.2 : LPSDR X 32..................................................................................................................................64 12.ORDERING INFORMATION .................................................................................................... 65 13. REVISION HISTORY ............................................................................................................... 66 |
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