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W641GG2JB-14 Datasheet(PDF) 6 Page - Winbond |
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W641GG2JB-14 Datasheet(HTML) 6 Page - Winbond |
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6 / 109 page  W641GG2JB 1-Gbit GDDR3 Graphics SDRAM Publication Release Date: Apr, 22, 2011 - 6 - Revision A01-002 1. GENERAL DESCRIPTION The W641GG2JB 1-Gbit GDDR3 GRAPHICS SDRAM is a high speed dynamic random-access memory designed for applications requiring high bandwidth. It contains 1,073,741,824 bits. The device can be configured to operate in two different modes: • in 2-CS mode the chip is organized as two 512 Mbit memories of 8 banks each, with 4096 row locations and 512 column locations per bank. • in 1-CS mode the chip is organized as one 1 Gbit memory, with 8192 row locations and 512 column locations per bank. The GDDR3 GRAPHICS SDRAM uses a double data rate architecture to achieve high speed operation. The double data rate architecture is essentially a 4n prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the GDDR3 GRAPHICS SDRAM effectively consists of a 4n data transfer every two clock cycles at the internal DRAM core and four corresponding n-bit wide, one-half-clock- cycle data transfers at the I/O pins. Unidirectional data strobes are transmitted externally, along with data, for use in data capture at the receiver. RDQS is a strobe transmitted by the GDDR3 GRAPHICS SDRAM during READs. WDQS is the data strobe sent by the memory controller during WRITEs. RDQS is edge-aligned with data for READs and WDQS is center-aligned with data for WRITEs. The GDDR3 GRAPHICS SDRAM operates from a differential clock (CLK and CLK#; the crossing of CLK going High and CLK# going Low will be referred to as the positive CLK edge). Commands (address and control signals) are registered at the positive CLK edge. Input data is registered at both edges of WDQS, and output data is referenced to both edges of RDQS, as well as to both edges of CLK. Read and write accesses to the GDDR3 GRAPHICS SDRAM are burst oriented. The burst length can be programmed to 4 or 8 and the two least significant bits of the burst address are ―Don‘t Care‖ and internally set to LOW. Accesses start at a selected location and continue for a total of four or eight locations. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and the row to be accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and the starting column location for the burst access. |
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