32M-BIT 3.0-VOLT PARALLEL FLASH MEMORY WITH PAGE MODE ( 66 Page)
The device operation can be initiated by writing specific address and data commands or sequences
into the instruction register. The device will be reset to reading array data when writing incorrect
address and data values or writing them in the improper sequence.
The addresses will be latched on the falling edge of #WE or #CE, whichever happens later; while the
data will be latched on the rising edge of #WE or #CE, whichever happens first. Please refer to timing
7.2.1 Reading Array Data
The default state after power up or a reset operation is the Read mode.
To execute a read operation, the chip is enabled by setting #CE and #OE active and #WE high. At the
same time, the required address or status register location is provided on the address lines. The
system reads the addressed location contents on the Data IO pins after the t
requirements have been met. Output data will not be accessible on the Data IO pins if either the
device or it’s outputs are not enabled by #CE or #OE being High, and the outputs will remain in a tri-
When the device completes an embedded memory operation (i.e., Program, automatic Chip Erase or
Sector Erase) successfully, it will return to the Read mode and from any address in the memory array
the data can be read. However, If the embedded operation fails to complete, by verifying the status
register bit DQ5 (exceeds time limit flag) going high during the operations, at this time system should
execute a Reset operation causing the device to return to Read mode.
Some operating states require a reset operation to return to Read mode such as:
Time-out condition during a program or erase failed condition, indicated by the status register
bit DQ5 going High during the operation. Failure during either of these states will prevent the
device from automatically returning to Read mode.
During device Auto Select mode or CFI mode, a reset operation is required to terminate their
In the above two situations, the device will not return to the Read mode unless a reset operation is
executed (either hardware reset or software reset instruction) or the system will not be able to read
The device will enter Erase-Suspended Read mode if the device receives an Erase Suspend
instruction while in the Sector Erase state. The erase operation will pause (after a time delay not
exceeding 20µs) prior to entering Erase-Suspend Read mode. At this time data can be programmed
or read from any sector that is not being erased. Another way to verify device status is to read the
addresses inside the sectors being erased. This will only provide the contents of the status register.
Program operation during Erase-Suspend Read mode of valid sector(s) will automatically return to the
Erase-Suspend Read mode upon successful completion of the program operation.
An Erase Resume instruction must be executed to exit the Erase-Suspended Read mode, at which
time suspended erase operations will resume. Erase operation will resume where it left off and
continue until successful completion unless another Erase Suspend instruction is received.
7.2.2 Page Mode Read
The Page Mode Read has page sizes of 16 bytes or 8 words. The higher addresses A[20:3] accesses
the desired page. To access a particular word or byte in a page, it is selected by A[2:0] for word mode
and A[2:0,A-1] for byte mode. Page mode can be turned on by keeping “page-read address” constant
and changing the “intra-read page” addresses. The page access time is t
, followed by t
the page read time. When #CE toggles, access time is t
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